MC68HC908GP32CP Freescale Semiconductor, MC68HC908GP32CP Datasheet - Page 145

• Manufacturer Part Number: MC68HC908GP32CP
• Description: IC MCU 8MHZ 32K FLASH 40-DIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908GP32CP

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 33
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• For Use With: M68EVB908GP32 - BOARD EVALUATION FOR HC908GP32
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

9.4 I/O Signals
9.4.1 CGMXCLK
9.4.2 STOP Instruction
MC68HC908GP32
MOTOROLA
NOTE:
NOTE:
•
MC68HC08GP32
The COP counter is a free-running 6-bit counter preceded by a 12-bit
prescaler counter. If not cleared by software, the COP counter overflows
and generates an asynchronous reset after 2
CGMXCLK cycles, depending on the state of the COP rate select bit,
COPRS, in the configuration register. With a 2
overflow option, a 32.768-kHz crystal gives a COP timeout period of
250 ms. Writing any value to location $FFFF before an overflow occurs
prevents a COP reset by clearing the COP counter and stages 12
through 5 of the prescaler.
Service the COP immediately after reset and before entering or after
exiting stop mode to guarantee the maximum time before the first COP
counter overflow.
A COP reset pulls the RST pin low for 32 CGMXCLK cycles and sets the
COP bit in the reset status register (RSR).
In monitor mode, the COP is disabled if the RST pin or the IRQ is held
at V
Place COP clearing instructions in the main program and not in an
interrupt subroutine. Such an interrupt subroutine could keep the COP
from generating a reset even while the main program is not working
properly.
The following paragraphs describe the signals shown in
CGMXCLK is the crystal oscillator output signal. CGMXCLK frequency
is equal to the crystal frequency.
The STOP instruction clears the COP prescaler.
TST
. During the break state, V
—
Computer Operating Properly (COP)
Rev. 6
TST
on the RST pin disables the COP.
Computer Operating Properly (COP)
18
13
– 2
– 2
4
4
or 2
CGMXCLK cycle
13
Figure
– 2
Technical Data
4
I/O Signals
9-1.
143