MC68HC908GP32CP Freescale Semiconductor, MC68HC908GP32CP Datasheet - Page 140
MC68HC908GP32CP
Manufacturer Part Number
MC68HC908GP32CP
Description
IC MCU 8MHZ 32K FLASH 40-DIP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC68HC908GP32CFB.pdf
(410 pages)
Specifications of MC68HC908GP32CP
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
33
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
For Use With
M68EVB908GP32 - BOARD EVALUATION FOR HC908GP32
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Manufacturer
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Company:
Part Number:
MC68HC908GP32CP
Manufacturer:
ROCKWELL
Quantity:
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Part Number:
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Manufacturer:
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Configuration Register (CONFIG)
Technical Data
138
NOTE:
Note: LVI5OR3 bit is only reset via POR (power-on reset)
Address:
Address:
On a FLASH device, the options except LVI5OR3 are one-time writeable
by the user after each reset. The LVI5OR3 bit is one-time writeable by
the user only after each POR (power-on reset). The CONFIG registers
are not in the FLASH memory but are special registers containing one-
time writeable latches after each reset. Upon a reset, the CONFIG
registers default to predetermined settings as shown in
Figure
OSCSTOPENB— Oscillator Stop Mode Enable Bar Bit
Reset:
Reset:
Read:
Write:
Read:
Write:
OSCSTOPENB enables the oscillator to continue operating during
stop mode. Setting the OSCSTOPENB bit allows the oscillator to
operate continuously even during stop mode. This is useful for driving
the timebase module to allow it to generate periodic wakeup while in
stop mode. (See
3.6.2 Stop
1 = Oscillator enabled to operate during stop mode
0 = Oscillator disabled during stop mode (default)
8-2.
COPRS
$001E
$001F
Bit 7
Bit 7
Figure 8-1. Configuration Register 2 (CONFIG2)
Figure 8-2. Configuration Register 1 (CONFIG1)
0
0
0
Configuration Register (CONFIG)
Mode.)
= Unimplemented
LVISTOP LVIRSTD LVIPWRD LVI5OR3
6
0
0
6
0
3.6 Clock Generator Module (CGM)
5
0
0
5
0
MC68HC908GP32
4
0
0
4
0
See Note
3
0
0
3
SSREC
•
MC68HC08GP32
2
0
0
2
0
STOPENB
Figure 8-1
STOP
OSC-
subsection
1
0
1
0
MOTOROLA
—
SCIBD-
COPD
SRC
Bit 0
Bit 0
Rev. 6
0
0
and
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