MC68HC908GP32CP Freescale Semiconductor, MC68HC908GP32CP Datasheet - Page 132

IC MCU 8MHZ 32K FLASH 40-DIP

MC68HC908GP32CP

Manufacturer Part Number
MC68HC908GP32CP
Description
IC MCU 8MHZ 32K FLASH 40-DIP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC68HC908GP32CP

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
33
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
For Use With
M68EVB908GP32 - BOARD EVALUATION FOR HC908GP32
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

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Manufacturer
Quantity
Price
Part Number:
MC68HC908GP32CP
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Quantity:
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Part Number:
MC68HC908GP32CP
Manufacturer:
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Clock Generator Module (CGMC)
7.6.6 PLL Reference Divider Select Register
Technical Data
130
NOTE:
NOTE:
NOTE:
Address:
PMDS may be called PRDS on other HC08 derivatives.
The PLL reference divider select register (PMDS) contains the
programming information for the modulo reference divider.
RDS3–RDS0 — Reference Divider Select Bits
The reference divider select bits have built-in protection such that they
cannot be written when the PLL is on (PLLON = 1).
The default divide value of 1 is recommended for all applications.
Bit7–Bit4 — Unimplemented Bits
Reset:
Read:
Write:
These read/write bits control the modulo reference divider that selects
the reference division factor, R. (See
Programming the
PLLON bit in the PCTL is set. A value of $00 in the reference divider
select register configures the reference divider the same as a value of
$01. (See
initializes the register to $01 for a default divide value of 1.
These bits have no function and always read as logic 0s.
Figure 7-9. PLL Reference Divider Select Register (PMDS)
$003B
Bit 7
0
0
Clock Generator Module (CGMC)
7.4.7 Special Programming
= Unimplemented
6
0
0
PLL.) RDS7–RDS0 cannot be written when the
5
0
0
MC68HC908GP32
4
0
0
7.4.3 PLL Circuits
RDS3
3
0
Exceptions.) Reset
RDS2
MC68HC08GP32
2
0
RDS1
1
0
and
MOTOROLA
7.4.6
RDS0
Bit 0
Rev. 6
1

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