EZ80F91NA050SC Zilog, EZ80F91NA050SC Datasheet - Page 321
EZ80F91NA050SC
Manufacturer Part Number
EZ80F91NA050SC
Description
IC ACCLAIM MCU 256KB 144-BGA
Manufacturer
Zilog
Series
eZ80® Acclaim!®r
Specifications of EZ80F91NA050SC
Core Processor
Z8
Core Size
8-Bit
Speed
50MHz
Connectivity
Ethernet, I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
144-LBGA
Data Bus Width
8 bit
Maximum Clock Frequency
50 MHz
Data Ram Size
16 KB
Number Of Programmable I/os
32
Number Of Timers
16 Bit
Operating Supply Voltage
3 V to 3.6 V
Mounting Style
SMD/SMT
Height
1.5 mm
Length
13 mm
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Width
13 mm
For Use With
269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
No RoHS Version Available
Other names
269-3251
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Table 197. EMAC Hash Table Register (EMAC_HTBL_0 = 0033h, EMAC_HTBL_1 = 0034h,
EMAC_HTBL_2 = 0035h, EMAC_HTBL_3 = 0036h, EMAC_HTBL_4 = 0037h, EMAC_HTBL_5
= 0038h, EMAC_HTBL_6 = 0039h, EMAC_HTBL_7 = 003Ah)
PS019215-0910
Bit
EMAC_HTBL_0 Reset
EMAC_HTBL_1 Reset
EMAC_HTBL_2 Reset
EMAC_HTBL_3 Reset
EMAC_HTBL_4 Reset
EMAC_HTBL_5 Reset
EMAC_HTBL_6 Reset
EMAC_HTBL_7 Reset
CPU Access
Note: R/W = Read/Write
Bit
Position
[7:0]
EMAC_HTBL_x
EMAC Hash Table Register
The EMAC Hash Table Register represents the 8x8 hash table matrix. This table is used as
an option to select between different multicast addresses. If a multicast address is
received, the first 6 bits of the CRC are decoded and added to a table that points to a single
bit within the hash table matrix. If the selected bit = 1, the multicast packet is accepted. If
the bit = 0, the multicast packet is rejected. See
Value
00h–
FFh
R/W
Description
This field is the hash table. The 64 bit hash table is
{EMAC_HTBL_7, EMAC_HTBL_6, EMAC_HTBL_5,
EMAC_HTBL_4, EMAC_HTBL_3, EMAC_HTBL_2,
EMAC_HTBL_1, EMAC_HTBL_0}.
7
0
0
0
0
0
0
0
0
R/W
6
0
0
0
0
0
0
0
0
R/W
5
0
0
0
0
0
0
0
0
R/W
4
0
0
0
0
0
0
0
0
R/W
3
0
0
0
0
0
0
0
0
Table
R/W
2
0
0
0
0
0
0
0
0
197.
Ethernet Media Access Controller
R/W
1
0
0
0
0
0
0
0
0
Product Specification
R/W
0
0
0
0
0
0
0
0
0
312
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