EZ80F91NA050SC Zilog, EZ80F91NA050SC Datasheet - Page 141
EZ80F91NA050SC
Manufacturer Part Number
EZ80F91NA050SC
Description
IC ACCLAIM MCU 256KB 144-BGA
Manufacturer
Zilog
Series
eZ80® Acclaim!®r
Specifications of EZ80F91NA050SC
Core Processor
Z8
Core Size
8-Bit
Speed
50MHz
Connectivity
Ethernet, I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
144-LBGA
Data Bus Width
8 bit
Maximum Clock Frequency
50 MHz
Data Ram Size
16 KB
Number Of Programmable I/os
32
Number Of Timers
16 Bit
Operating Supply Voltage
3 V to 3.6 V
Mounting Style
SMD/SMT
Height
1.5 mm
Length
13 mm
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Width
13 mm
For Use With
269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
No RoHS Version Available
Other names
269-3251
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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PS019215-0910
Timer Control Register
The Timer x Control Register (see
enabling the timer, selecting the clock source, selecting the clock divider, selecting
between CONTINUOUS and SINGLEPASS modes, and enabling the auto-reload
feature.
Table 54. Timer Control Register
TMR2_CTL = 006Fh, TMR3_CTL = 0074h)
Bit
Reset
CPU Access
Note: R = Read only; R/W = Read/Write.
Bit
Position
7
BRK_STOP
[6:5]
CLK_SEL
[4:3]
CLK_DIV
2
TIM_CONT
Value
0
1
00
01
10
11
00
01
10
11
0
1
Timer source is the system clock divided by the prescaler.
System clock divider = 4.
System clock divider = 16.
System clock divider = 64.
Description
The timer continues to operate during debug break points.
The timer stops operation and holds count value during debug
break points.
Timer source is the Real Time Clock Input.
Timer source is the Event Count (ECx) input—falling edge.
For Timer 1 this is EC0.
For Timer 2, this is EC1.
Timer source is the Event Count (ECx) input—rising edge.
For Timer 1 this is EC0.
For Timer 2, this is EC1.
System clock divider = 256.
The timer operates in SINGLE PASS mode. TIM_EN (bit 0) is
reset to 0 and counting stops when the end-of-count value is
reached.
The timer operates in CONTINUOUS mode. The timer reload
value is written to the counter when the end-of-count value is
reached.
R/W
7
0
R/W
Table
6
0
(TMR0_CTL = 0060h, TMR1_CTL = 0065h,
54) is used to control timer operations including
R/W
5
0
R/W
4
0
R/W
3
0
Programmable Reload Timers
Product Specification
R/W
2
0
eZ80F91 MCU
R/W
1
0
R/W
0
0
132
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