EZ80F91NA050SC Zilog, EZ80F91NA050SC Datasheet - Page 222
EZ80F91NA050SC
Manufacturer Part Number
EZ80F91NA050SC
Description
IC ACCLAIM MCU 256KB 144-BGA
Manufacturer
Zilog
Series
eZ80® Acclaim!®r
Specifications of EZ80F91NA050SC
Core Processor
Z8
Core Size
8-Bit
Speed
50MHz
Connectivity
Ethernet, I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
144-LBGA
Data Bus Width
8 bit
Maximum Clock Frequency
50 MHz
Data Ram Size
16 KB
Number Of Programmable I/os
32
Number Of Timers
16 Bit
Operating Supply Voltage
3 V to 3.6 V
Mounting Style
SMD/SMT
Height
1.5 mm
Length
13 mm
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Width
13 mm
For Use With
269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
No RoHS Version Available
Other names
269-3251
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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eZ80F91 MCU
Product Specification
213
Transferring Data
Byte Format
Every character transferred on the SDA line must be a single 8-bit byte. The number of
bytes that is transmitted per transfer is unrestricted. Each byte must be followed by an
Acknowledge (ACK). Data is transferred with the most-significant bit (msb) first.
Figure 45
displays a receiver that holds the SCL line Low to force the transmitter into a
Wait state. Data transfer then continues when the receiver is ready for another byte of data
and releases SCL.
SDA Signal
MSB
Acknowledge from
Acknowledge from
Receiver
Receiver
SCL Signal
1
2
8
9
1
9
S
P
ACK
START Condition
STOP Condition
Clock Line Held Low By Receiver
2
Figure 45. I
C Frame Structure
Acknowledge
Data transfer with an ACK function is obligatory. The ACK-related clock pulse is gen-
erated by the master. The transmitter releases the SDA line (High) during the ACK
clock pulse. The receiver must pull down the SDA line during the ACK clock pulse so
that it remains stable (Low) during the High period of this clock pulse. See
Figure 46
on page 214.
A receiver that is addressed is obliged to generate an ACK after each byte is received.
When a slave receiver does not acknowledge the slave address (for example, unable to
receive because it is performing some real-time function), the data line must be left High
by the slave. The master then generates a STOP condition to abort the transfer.
If a slave receiver acknowledges the slave address, but cannot receive any more data
bytes, the master must abort the transfer. The abort is indicated by the slave generating the
Not Acknowledge (NACK) on the first byte to follow. The slave leaves the data line High
and the master generates the STOP condition.
If a master receiver is involved in a transfer, it must signal the end of the data stream to the
slave transmitter by not generating an ACK on the final byte that is clocked out of the
slave. The slave transmitter must release the data line to allow the master to generate a
STOP or a repeated START condition.
2
PS019215-0910
I
C Serial I/O Interface
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