EZ80F91NA050SC Zilog, EZ80F91NA050SC Datasheet - Page 262
EZ80F91NA050SC
Manufacturer Part Number
EZ80F91NA050SC
Description
IC ACCLAIM MCU 256KB 144-BGA
Manufacturer
Zilog
Series
eZ80® Acclaim!®r
Specifications of EZ80F91NA050SC
Core Processor
Z8
Core Size
8-Bit
Speed
50MHz
Connectivity
Ethernet, I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
144-LBGA
Data Bus Width
8 bit
Maximum Clock Frequency
50 MHz
Data Ram Size
16 KB
Number Of Programmable I/os
32
Number Of Timers
16 Bit
Operating Supply Voltage
3 V to 3.6 V
Mounting Style
SMD/SMT
Height
1.5 mm
Length
13 mm
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Width
13 mm
For Use With
269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
No RoHS Version Available
Other names
269-3251
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Table 146. ZDI Status Register
PS019215-0910
Bit
Reset
CPU Access
Note: R = Read Only.
Bit
Position
7
zdi_active
6
5
halt_SLP
4
ADL
3
MADL
2
IEF1
[1:0]
Reserved
ZDI Status Register
The ZDI Status register provides current information on the eZ80F91 device and the CPU.
See
Table
Value Description
0
1
0
0
1
0
1
0
1
0
1
00
146.
R
7
0
The CPU is not functioning in ZDI mode.
The CPU is currently functioning in ZDI mode.
Reserved.
The CPU is not currently in HALT or SLEEP mode.
The CPU is currently in HALT or SLEEP mode.
The CPU is operating in Z80
(ADL bit = 0)
The CPU is operating in ADL MEMORY mode.
(ADL bit = 1)
The CPU’s Mixed-Memory mode (MADL) bit is reset to 0.
The CPU’s Mixed-Memory mode (MADL) bit is set to 1.
The CPU’s Interrupt Enable Flag 1 is reset to 0. Maskable
interrupts are disabled.
The CPU’s Interrupt Enable Flag 1 is set to 1. Maskable
interrupts are enabled.
Reserved.
R
(ZDI_STAT = 03h in the ZDI Register Read Only Address Space)
6
0
R
5
0
R
4
0
®
R
3
0
MEMORY mode.
R
2
0
R
1
0
Product Specification
R
0
0
Zilog Debug Interface
eZ80F91 MCU
253
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