EZ80F91NA050SC Zilog, EZ80F91NA050SC Datasheet - Page 114
EZ80F91NA050SC
Manufacturer Part Number
EZ80F91NA050SC
Description
IC ACCLAIM MCU 256KB 144-BGA
Manufacturer
Zilog
Series
eZ80® Acclaim!®r
Specifications of EZ80F91NA050SC
Core Processor
Z8
Core Size
8-Bit
Speed
50MHz
Connectivity
Ethernet, I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
144-LBGA
Data Bus Width
8 bit
Maximum Clock Frequency
50 MHz
Data Ram Size
16 KB
Number Of Programmable I/os
32
Number Of Timers
16 Bit
Operating Supply Voltage
3 V to 3.6 V
Mounting Style
SMD/SMT
Height
1.5 mm
Length
13 mm
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Width
13 mm
For Use With
269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
No RoHS Version Available
Other names
269-3251
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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PS019215-0910
Flash Control Register
The Flash Control register enables or disables memory access to Flash memory. I/O access
to the Flash control registers and to Flash memory is still possible while Flash memory
space access is disabled.
The minimum access time of internal Flash memory is 60 ns. The Flash Control Regis-
ter must be configured to provide the appropriate number of wait states based on the sys-
tem clock frequency of the eZ80F91 device. Because the maximum SCLK frequency is
50 MHz (20 ns), the default on RESET is for four Wait states to be inserted for Flash
memory access (Flash memory access + one eZ80
80 ns ÷ 20 ns = 4 Wait states). See
Table 38. Flash Control Register
Bit
Reset
CPU Access
Note: R/W = Read/Write, R = Read Only.
Bit Position
[7:5]
FLASH_WAIT
[4]
[3]
FLASH_EN
[2:0]
Value Description
000
001
010
011
100
101
110
111
0
0
1
000
R/W
0 wait states are inserted when the Flash is active.
1 wait state is inserted when the Flash is active.
2 wait states are inserted when the Flash is active.
3 wait states are inserted when the Flash is active.
4 wait states are inserted when the Flash is active.
5 wait states are inserted when the Flash is active.
6 wait states are inserted when the Flash is active.
7 wait states are inserted when the Flash is active.
Reserved.
Flash memory access is disabled.
Flash memory access is enabled.
Reserved.
7
1
R/W
Table
6
0
(FLASH_CTRL = 00F8h)
38.
R/W
5
0
®
Bus Cycle = 60 ns + 20 ns = 80 ns;
R
4
0
R/W
3
1
Product Specification
R
2
0
eZ80F91 MCU
R
1
0
Flash Memory
R
0
0
105
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