EZ80F91NA050SC Zilog, EZ80F91NA050SC Datasheet - Page 300

• Manufacturer Part Number: EZ80F91NA050SC
• Description: IC ACCLAIM MCU 256KB 144-BGA
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F91NA050SC

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 144-LBGA
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 50 MHz
• Data Ram Size: 16 KB
• Number Of Programmable I/os: 32
• Number Of Timers: 16 Bit
• Operating Supply Voltage: 3 V to 3.6 V
• Mounting Style: SMD/SMT
• Height: 1.5 mm
• Length: 13 mm
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Width: 13 mm
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: No RoHS Version Available
• Other names: 269-3251

PS019215-0910
the RxFIFO and writes them into the Rx descriptor status LSB and MSB. The packet-
length counter is stored into the descriptor table’s Packet Length field, and the descriptor
table’s next pointer is written into the Rx descriptor table. Additionally, the
Rx_DONE_STAT bit in the EMAC Interrupt Status Register is set to 1.
Signal Termination
When the EMAC interface is not used, the MII signals must be terminated as listed in
Table
MDIO is controlled by the MDC output signal. When the EMAC is not being used, these
two pins are not driven. The RX_DV, RX_ER, and RXD[3:0] inputs are controlled by the
rising edge of the RX_CLK input signal. When RX_CLK is tied to Ground, these pins do
not affect the EMAC. The TX_EN, TX_ER, and TXD[3:0] outputs are controlled by the
rising edge of the TX_CLK input signal. When TX_CLK is tied to Ground, these pins do
not affect the EMAC. The CRS and COL input pins have no relationship to the clock, and
therefore must be placed into nonactive states and tied to Ground.
Table 175. MII Signal Termination When EMAC is Not Used
Signal
MDIO
MDC
RX_DV
CRS
RX_CLK
RX_ER
RXD[3:0]
COL
TX_CLK
TX_EN
TXD[3:0]
TX_ER
175. Terminated pins are either left unconnected (float) or tied to ground.
Pin Type
Bidirectional
Output pin
Input pin
Input pin
Input pin
Input pin
Input pins
Input pin
Input pin
Output pin
Output pins
Output pin
Termination
Direction
Float
Float
Float
Ground
Ground
Float
Float
Ground
Ground
Float
Float
Float
Ethernet Media Access Controller
Product Specification
291