EZ80F91NA050SC Zilog, EZ80F91NA050SC Datasheet - Page 115
EZ80F91NA050SC
Manufacturer Part Number
EZ80F91NA050SC
Description
IC ACCLAIM MCU 256KB 144-BGA
Manufacturer
Zilog
Series
eZ80® Acclaim!®r
Specifications of EZ80F91NA050SC
Core Processor
Z8
Core Size
8-Bit
Speed
50MHz
Connectivity
Ethernet, I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
144-LBGA
Data Bus Width
8 bit
Maximum Clock Frequency
50 MHz
Data Ram Size
16 KB
Number Of Programmable I/os
32
Number Of Timers
16 Bit
Operating Supply Voltage
3 V to 3.6 V
Mounting Style
SMD/SMT
Height
1.5 mm
Length
13 mm
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Width
13 mm
For Use With
269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
No RoHS Version Available
Other names
269-3251
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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PS019215-0910
Flash Frequency Divider Register
The 8-bit frequency divider allows the programming of Flash memory over a range of
system clock frequencies. Flash is programmed with system clock frequencies ranging
from 154 kHz to 50 MHz. The Flash controller requires an input clock with a period that
falls within the range of 5.16.5 µs. The period of the Flash controller clock is set in the
Flash Frequency Divider Register. Writes to this register is allowed only after it is
unlocked via the FLASH_KEY register. The Flash Frequency Divider Register value
required versus the system clock frequency is listed in
outside of the ranges shown are not supported. Register values for the Flash Frequency
Divider are listed in
Table 39. Flash Frequency Divider Values
Table 40. Flash Frequency Divider Register
System Clock Frequency
154–196 kHz
308–392 kHz
462–588 kHz
616 kHz–50 MHz
Note: *The CEILING function rounds fractional values up to the next whole number. For example,
Bit
Reset
CPU Access
Note: R/W = Read/Write, R = Read Only. *Key sequence required to enable Writes
Bit Position
[7:0]
FLASH_FDIV
CEILING(3.01) is 4.
Value
01h–FFh Divider value for generating the required 5.1-6.5 µs Flash
Table
R/W*
40.
7
0
Description
controller clock period.
Flash Frequency Divider Value
1
2
3
CEILING [System Clock Frequency (MHz) x 5.1 (µs)]*
R/W*
6
0
R/W*
5
0
R/W*
(FLASH_FDIV = 00F9h)
4
0
Table
R/W*
39. System clock frequencies
3
0
Product Specification
R/W*
2
0
eZ80F91 MCU
R/W*
1
0
Flash Memory
R/W
0
1
106
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