EZ80F91NA050SC Zilog, EZ80F91NA050SC Datasheet - Page 306
EZ80F91NA050SC
Manufacturer Part Number
EZ80F91NA050SC
Description
IC ACCLAIM MCU 256KB 144-BGA
Manufacturer
Zilog
Series
eZ80® Acclaim!®r
Specifications of EZ80F91NA050SC
Core Processor
Z8
Core Size
8-Bit
Speed
50MHz
Connectivity
Ethernet, I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
144-LBGA
Data Bus Width
8 bit
Maximum Clock Frequency
50 MHz
Data Ram Size
16 KB
Number Of Programmable I/os
32
Number Of Timers
16 Bit
Operating Supply Voltage
3 V to 3.6 V
Mounting Style
SMD/SMT
Height
1.5 mm
Length
13 mm
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Width
13 mm
For Use With
269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
No RoHS Version Available
Other names
269-3251
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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PS019215-0910
EMAC Operation in HALT Modes
EMAC Registers
transfer capabilities at certain system operating frequencies, you must first understand the
internal data bus bandwidth that is required under ideal conditions.
For 10 BaseT Ethernet connectivity, the data rate is 10 Mbps, which equates to 1.25 Mbps.
If the eZ80F91 MCU is operating in FULL-DUPLEX mode over 10BaseT, the data rate for
RX data and TX data is 1.25 Mbps. Because raw data transfers at this rate consume a cer-
tain amount of CPU bandwidth, the CPU must support traffic from both directions as well
as operate at a minimum clock frequency of (1.25 + 1.25) * 2 = 5 MHz while transferring
Ethernet packets to and from the physical layer.
Similarly, for 100 BaseT Ethernet, the data rate is 100 Mbps, which equates to 12.5 Mbps.
If the eZ80F91 MCU is operating in FULL-DUPLEX mode over 100 BaseT, the data rate
for RX data and TX data is 12.5 Mbps. Because raw data transfers at this rate consume a
certain amount of CPU bandwidth, the CPU must support traffic from both directions as
well as operate at a minimum clock frequency of (12.5 + 12.5) x 2 = 50 MHz while trans-
ferring Ethernet packets to and from the physical layer. Consequently, 50 MHz is the min-
imum system clock speed that the eZ80
while not including any software overhead or additional eZ80 tasks.
The FIFO functionality of the EMAC operates at any frequency as long as the user appli-
cation avoids overrun and underrun errors via higher-level flow control. Actual applica-
tion requirements will dictate Ethernet modes of operation (FULL-DUPLEX, HALF-
DUPLEX, etc.). Because each user and application is different, it becomes your responsi-
bility to control the data flow with these parameters. Under ideal conditions, the system
clock will operate somewhere between 5 MHz and 50 MHz to handle the EMAC data
rates.
When the CPU is in HALT mode, the eZ80F91 device’s EMAC block cannot be disabled
as other peripherals. Upon receipt of an Ethernet packet, a maskable Receive interrupt is
generated by the EMAC block, just as it would be in a non-halt mode. Accordingly, the
processor wakes up and continues with the user-defined application.
After a system reset, all EMAC registers are set to their default values. Any Writes to
unused registers or register bits are ignored and reads return a value of 0. For compatibil-
ity with future revisions, unused bits within a register must always be written with a value
of 0. Read/Write attributes, reset conditions, and bit descriptions of all of the EMAC reg-
isters are provided in this section.
®
CPU requires to sustain EMAC data transfers
Ethernet Media Access Controller
Product Specification
297
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