ADUC836BS Analog Devices Inc, ADUC836BS Datasheet - Page 65

• Manufacturer Part Number: ADUC836BS
• Description: IC ADC DUAL 16BIT W/MCU 52-MQFP
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC8xxr

Specifications of ADUC836BS

• Rohs Status: RoHS non-compliant
• Core Processor: 8052
• Core Size: 8-Bit
• Speed: 12.58MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: POR, PSM, PWM, Temp Sensor, WDT
• Number Of I /o: 34
• Program Memory Size: 62KB (62K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.25 V
• Data Converters: A/D 7x16b; D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 52-MQFP, 52-PQFP

Power Saving Modes
Setting the Idle and Power-Down Mode Bits, PCON.0 and
PCON.1, respectively, in the PCON SFR described in Table II
allows the chip to be switched from Normal mode into Idle
mode, and also into full Power-Down mode.
In Idle mode, the oscillator continues to run, but the core clock
generated from the PLL is halted. The on-chip peripherals
continue to receive the clock and remain functional. The CPU
status is preserved with the stack pointer, program counter, and
all other internal registers maintain their data during Idle mode.
Port pins and DAC output pins also retain their states, and ALE
and PSEN outputs go high in this mode. The chip will recover
from Idle mode upon receiving any enabled interrupt, or upon
receiving a hardware reset.
In Power-Down mode, both the PLL and the clock to the core are
stopped.The on-chip oscillator can be halted or can continue to
oscillate, depending on the state of the oscillator power-down bit
(OSC_PD) in the PLLCON SFR.The TIC, being driven directly
from the oscillator, can also be enabled during power-down. All
other on-chip peripherals, however, are shut down. Port pins retain
their logic levels in this mode, but the DAC output goes to a high
impedance state (three-state) while ALE and PSEN outputs are
held low. During full Power-Down mode with the oscillator and
wake-up timer running, the ADuC836 typically consumes a total
of 15 A.There are five ways of terminating Power-Down mode:
Asserting the RESET Pin (Pin 15)
Returns to Normal mode. All registers are set to their reset default
value and program execution starts at the reset vector once the
RESET pin is deasserted.
Cycling Power
All registers are set to their default state and program execution
starts at the reset vector approximately 128 ms later.
Time Interval Counter (TIC) Interrupt
If the OSC_PD bit in the PLLCON SFR is clear, the 32 kHz
oscillator will remain powered up even in Power-Down mode.
If the Time Interval Counter (Wakeup/RTC timer) is enabled,
a TIC interrupt will wake the ADuC836 up from Power-Down
mode. The CPU services the TIC interrupt. The RETI at the end
of the TIC ISR will return the core to the instruction after the
one that enabled power-down.
SPI Interrupt
If the SERIPD bit in the PCON SFR is set, then an SPI interrupt,
if enabled, will wake up the ADuC836 from Power-Down mode.
The CPU services the SPI interrupt.The RETI at the end of the
ISR will return the core to the instruction after the one that enabled
power-down.
INT0 Interrupt
If the INT0PD bit in the PCON SFR is set, an external interrupt 0,
if enabled, will wake up the ADuC836 from power-down. The
CPU services the SPI interrupt. The RETI at the end of the ISR
will return the core to the instruction after the one that enabled
power-down.
REV. A
–65–
Wake-Up from Power-Down Latency
Even with the 32 kHz crystal enabled during power-down, the PLL
will take some time to lock after a wake-up from power-down.Typ-
ically, the PLL will take about 1 ms to lock. During this time, code
will execute, but not at the specified frequency. Some operations
require an accurate clock, for example, UART communications,
to achieve specified 50 Hz/60 Hz rejection from the ADCs. The
following code may be used to wait for the PLL to lock:
WAITFORLOCK:
If the crystal has been powered down during power-down, there
is an additional delay associated with the startup of the crystal
oscillator before the PLL can lock. 32 kHz crystals are inherently
slow to oscillate, typically taking about 150 ms. Once again, during
this time before lock, code will execute, but the exact frequency
of the clock cannot be guaranteed. Again for any timing sensitive
operations, it is recommended to wait for lock using the lock bit
in PLLCON, as shown in the code above.
Grounding and Board Layout Recommendations
As with all high resolution data converters, special attention must
be paid to grounding and PC board layout of ADuC836 based
designs in order to achieve optimum performance from the ADCs
and DAC.
Although the ADuC836 has separate pins for analog and digital
ground (AGND and DGND), the user must not tie these to two
separate ground planes unless the two ground planes are con-
nected together very close to the ADuC836, as illustrated in the
simplified example of Figure 64a. In systems where digital and
analog ground planes are connected together somewhere else
(at the system’s power supply, for example), they cannot be con-
nected again near the ADuC836 since a ground loop would result.
In these cases, tie the ADuC836’s AGND and DGND pins all to
the analog ground plane, as illustrated in Figure 64b. In systems
with only one ground plane, ensure that the digital and analog com-
ponents are physically separated onto separate halves of the board
such that digital return currents do not flow near analog circuitry
and vice versa. The ADuC836 can then be placed between the
digital and analog sections, as illustrated in Figure 64c.
In all of these scenarios, and in more complicated real-life appli-
cations, keep in mind the flow of current from the supplies and
back to ground. Make sure the return paths for all currents are as
close as possible to the paths the currents took to reach their des-
tinations. For example, do not power components on the analog
side of Figure 64b with DV
rents from DV
currents flowing under analog circuitry, which could happen if
the user placed a noisy digital chip on the left half of the board
in Figure 64c.Whenever possible, avoid large discontinuities in
the ground plane(s) (such as those formed by a long trace on the
same layer), since they force return signals to travel a longer path.
And of course, make all connections directly to the ground plane
with little or no trace separating the pin from its via to ground.
MOV A, PLLCON
JNB ACC.6, WAITFORLOCK
DD
to flow through AGND. Also, try to avoid digital
DD
since that would force return cur-
ADuC836