ADUC836BS Analog Devices Inc, ADUC836BS Datasheet - Page 64

• Manufacturer Part Number: ADUC836BS
• Description: IC ADC DUAL 16BIT W/MCU 52-MQFP
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC8xxr

Specifications of ADUC836BS

• Rohs Status: RoHS non-compliant
• Core Processor: 8052
• Core Size: 8-Bit
• Speed: 12.58MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: POR, PSM, PWM, Temp Sensor, WDT
• Number Of I /o: 34
• Program Memory Size: 62KB (62K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.25 V
• Data Converters: A/D 7x16b; D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 52-MQFP, 52-PQFP

Power Supplies
The ADuC836’s operational power supply voltage range is 2.7 V
to 5.25 V. Although the guaranteed data sheet specifications are
given only for power supplies within 2.7 V to 3.6 V or +5% of the
nominal 5 V level, the chip will function equally well at any power
supply level between 2.7 V and 5.25 V.
Separate analog and digital power supply pins (AV
respectively) allow AV
signals that are often present on the system DV
the part can also operate with split supplies, that is, using different
voltage supply levels for each supply. For example, this means that
the system can be designed to operate with a DV
3 V while the AV
typical split-supply configuration is shown in Figure 61.
As an alternative to providing two separate power supplies, AV
can be kept quiet by placing a small series resistor and/or ferrite
bead between it and DV
to ground. An example of this configuration is shown in Figure 62.
In this configuration, other analog circuitry (such as op amps,
voltage reference, and so on) can be powered from the AV
supply line as well.
ADuC836
Figure 62. External Single-Supply Connections
Figure 61. External Dual-Supply Connections
DIGITAL SUPPLY
0.1F
0.1F
+
–
+
–
DIGITAL SUPPLY
DD
10F
level can be at 5 V, or vice-versa if required. A
DD
10F
DD
to be kept relatively free of noisy digital
, and then decoupling AV
20
34
48
21
35
47
20
48
47
34
21
35
DV
DGND
DV
DGND
BEAD
DD
DD
ADuC836
ADuC836
1.6
AGND
AGND
AV
AV
DD
ANALOG SUPPLY
DD
10F
DD
5
6
5
6
10F
DD
line. In this mode,
DD
0.1F
voltage level of
0.1F
DD
and DV
+
–
separately
DD
DD
DD
,
–64–
Notice that in Figures 61 and 62, a large value (10 F) reservoir
capacitor sits on DV
AV
each V
to include all of these capacitors and ensure the smaller capacitors
are closest to each V
Connect the ground terminal of each of these capacitors directly to
the underlying ground plane. Finally, it should also be noticed that,
at all times, the analog and digital ground pins on the ADuC836
should be referenced to the same system ground reference point.
Power-On Reset (POR) Operation
An internal POR (Power-On Reset) is implemented on the
ADuC836. For DV
the ADuC836 in reset. As DV
timer will time out for typically 128 ms before the part is
released from reset. The user must ensure that the power supply
has reached a stable 2.7 V minimum level by this time. Likewise
on power-down, the internal POR will hold the ADuC836 in
reset until the power supply has dropped below 1 V. Figure 63
illustrates the operation of the internal POR in detail.
Power Consumption
The DV
normal, idle, and power-down modes. The AV
current is specified with the analog peripherals disabled. The
normal mode power consumption represents the current drawn
from DV
(watchdog timer, power supply monitor, and so on) consume
negligible current and are therefore lumped in with the normal
operating current here. Of course, the user must add any currents
sourced by the parallel and serial I/O pins, and those sourced
by the DAC in order to determine the total current needed at the
ADuC836’s DV
from the DV
Flash/EE erase and program cycles.
DV
CORE RESET
DD
INTERNAL
DD
. Also, local decoupling capacitors (0.1 F) are located at
DD
Figure 63. Internal Power-on-Reset Operation
2.45V TYP
DD
1.0V TYP
DD
pin of the chip. As per standard design practice, be sure
power supply current consumption is specified in
by the digital core. The other on-chip peripherals
DD
supply will increase by approximately 5 mA during
DD
and AV
DD
DD
DD
128ms TYP
below 2.45 V, the internal POR will hold
pin with lead lengths as short as possible.
and a separate 10 F capacitor sits on
DD
DD
supply pins. Also, current drawn
rises above 2.45 V, an internal
128ms TYP
DD
power supply
1.0V TYP
REV. A