ADUC836BS Analog Devices Inc, ADUC836BS Datasheet - Page 47

• Manufacturer Part Number: ADUC836BS
• Description: IC ADC DUAL 16BIT W/MCU 52-MQFP
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC8xxr

Specifications of ADUC836BS

• Rohs Status: RoHS non-compliant
• Core Processor: 8052
• Core Size: 8-Bit
• Speed: 12.58MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: POR, PSM, PWM, Temp Sensor, WDT
• Number Of I /o: 34
• Program Memory Size: 62KB (62K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.25 V
• Data Converters: A/D 7x16b; D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 52-MQFP, 52-PQFP

The main features of the MicroConverter I
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Software Master Mode
The ADuC836 can be used as an I
the I
the data bit by bit, which is referred to as a software master. Master
mode is enabled by setting the I2CM bit in the I2CCON register.
To transmit data on the SDATA line, MDE must be set to enable
the output driver on the SDATA pin. If MDE is set, the SDATA
pin will be pulled high or low depending on whether the MDO
bit is set or cleared. MCO controls the SCLOCK pin and is
always configured as an output in Master mode. In Master mode,
the SCLOCK pin will be pulled high or low depending on the
whether MCO is set or cleared.
To receive data, MDE must be cleared to disable the output driver
on SDATA. Software must provide the clocks by toggling the
MCO bit and reading the SDATA pin via the MDI bit. If MDE
is cleared, MDI can be used to read the SDATA pin.The value of
the SDATA pin is latched into MDI on a rising edge of SCLOCK.
MDI is set if the SDATA pin was high on the last rising edge of
SCLOCK. MDI is clear if the SDATA pin was low on the last
rising edge of SCLOCK.
Software must control MDO, MCO, and MDE appropriately to
generate the START condition, slave address, acknowledge bits,
data bytes, and STOP conditions. These functions are provided
in Application Note uC001.
Hardware Slave Mode
After reset, the ADuC836 defaults to hardware Slave mode. The
I
Slave mode is enabled by clearing the I2CM bit in I2CCON.
The ADuC836 has a full hardware slave. In Slave mode, the I
address is stored in the I2CADD register. Data received or to be
transmitted is stored in the I2CDAT register.
REV. A
2
C interface is enabled by clearing the SPE bit in SPICON.
Only two bus lines are required: a serial data line (SDATA)
and a serial clock line (SCLOCK).
An I
Because each slave device has a unique 7-bit address, single
master/slave relationships can exist at all times even in a
multislave environment (Figure 35).
On-chip filtering rejects <50 ns spikes on the SDATA and
SCLOCK lines to preserve data integrity.
2
C peripheral in Master mode and writing software to output
2
C master can communicate with multiple slave devices.
Figure 35. Typical I
MASTER
I
2
C
DV
DD
2
C master device by configuring
2
C System
SLAVE #1
SLAVE #2
2
I
I
2
2
C interface are:
C
C
2
C
–47–
Once enabled in I
a START condition. If the ADuC836 detects a valid start con-
dition followed by a valid address, and by the R/W bit, the I2CI
interrupt bit will be automatically set by hardware.
The I
has preconfigured the I
as well as the global interrupt Bit EA in the IE SFR, i.e.,
On the ADuC836, an auto clear of the I2CI bit is implemented
so this bit is cleared automatically on a read or write access to the
I2CDAT SFR.
If for any reason the user tries to clear the interrupt more than
once, i.e., access the data SFR more than once per interrupt,
then the I
be reset using the I2CRS bit.
The user can choose to poll the I2CI bit or enable the interrupt.
In the case of the interrupt, the PC counter will vector to 003BH
at the end of each complete byte. For the first byte when the user
gets to the I2CI ISR, the 7-bit address and the R/W bit will appear
in the I2CDAT SFR.
The I2CTX bit contains the R/W bit sent from the master. If
I2CTX is set, the master would like to receive a byte. Therefore,
the slave will transmit data by writing to the I2CDAT register.
If I2CTX is cleared, the master would like to transmit a byte.
Therefore, the slave will receive a serial byte. The software can
interrogate the state of I2CTX to determine whether it should
write to or read from I2CDAT.
Once the ADuC836 has received a valid address, hardware will
hold SCLOCK low until the I2CI bit is cleared by the software.
This allows the master to wait for the slave to be ready before
transmitting the clocks for the next byte.
The I2CI interrupt bit will be set every time a complete data byte
is received or transmitted provided it is followed by a valid ACK.
If the byte is followed by a NACK, an interrupt is generated. The
ADuC836 will continue to issue interrupts for each complete
data byte transferred until a STOP condition is received or the
interface is reset.
When a STOP condition is received, the interface will reset to a
state where it is waiting to be addressed (idle). Similarly, if the
interface receives a NACK at the end of a sequence, it also returns
to the default idle state. The I2CRS bit can be used to reset the
I
the default idle state.
It should be noted that there is no way (in hardware) to distinguish
between an interrupt generated by a received START + valid
address and an interrupt generated by a received data byte. User
software must be used to distinguish between these interrupts.
2
C interface. This bit can be used to force the interface back to
; Enabling I2C Interrupts for the ADuC836
MOV IEIP2,#01h ; enable I2C interrupt
SETB EA
MOV I2CDAT, A ; I2CI auto-cleared
MOV A, I2CDAT ; I2CI auto-cleared
2
C peripheral will only generate a core interrupt if the user
2
C controller will halt. The interface will then have to
2
C Slave mode, the slave controller waits for
2
C interrupt enable bit in the IEIP2 SFR
ADuC836