AT90CAN128-16AI Atmel, AT90CAN128-16AI Datasheet - Page 266
AT90CAN128-16AI
Manufacturer Part Number
AT90CAN128-16AI
Description
IC MCU AVR FLASH 128K 64TQFP
Manufacturer
Atmel
Series
AVR® 90CANr
Specifications of AT90CAN128-16AI
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
CAN, EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
For Use With
ATDVK90CAN1 - KIT DEV FOR AT90CAN128 MCU
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT90CAN128-16AI
Manufacturer:
ALTERA
Quantity:
101
Company:
Part Number:
AT90CAN128-16AI
Manufacturer:
ATMEL
Quantity:
642
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19.11.5
19.11.6
19.12 Examples of CAN Baud Rate Setting
266
AT90CAN32/64/128
CAN Time Stamp Registers - CANSTML and CANSTMH
CAN Data Message Register - CANMSG
• Bit 31:3 – IDMSK28:0: Identifier Mask
• Bit 2 – RTRMSK: Remote Transmission Request Mask
• Bit 1 – Reserved Bit
Writing zero in this bit is recommended.
• Bit 0 – IDEMSK: Identifier Extension Mask
• Bits 15:0 - TIMSTM15:0: Time Stamp Count
CAN time stamp counter range 0 to 65,535.
• Bit 7:0 – MSG7:0: Message Data
This register contains the CAN data byte pointed at the page MOb register.
After writing in the page MOb register, this byte is equal to the specified message location of the
pre-defined identifier + index. If auto-incrementation is used, at the end of the data register writ-
ing or reading cycle, the index is auto-incremented.
The range of the counting is 8 with no end of loop (0, 1,..., 7, 0,...).
The CAN bus requires very accurate timing especially for high baud rates. It is recommended to
use only an external crystal for CAN operations.
(Refer to
257
Initial Value
Read/Write
Initial Value
Read/Write
to
Bit
Bit
Bit
– 0 - comparison true forced -
– 1 - bit comparison enabled -
– 0 - comparison true forced
– 1 - bit comparison enabled.
– 0 - comparison true forced
– 1 - bit comparison enabled.
page 258
“Bit Timing” on page 241
TIMSTM15 TIMSTM14 TIMSTM13 TIMSTM12 TIMSTM11 TIMSTM10 TIMSTM9 TIMSTM8 CANSTMH
TIMSTM7 TIMSTM6 TIMSTM5 TIMSTM4 TIMSTM3 TIMSTM2 TIMSTM1 TIMSTM0
MSG 7
15
R/W
R
7
-
7
-
for “CAN Bit Timing Registers”).
MSG 6
14
R/W
R
6
-
6
-
MSG 5
13
R/W
R
5
-
5
-
and
See “Acceptance Filter” on page 246.
See “Acceptance Filter” on page 246.
MSG 4
“Baud Rate” on page 242
R/W
12
R
4
-
4
-
MSG 3
R/W
11
R
3
-
3
-
MSG 2
R/W
10
R
2
-
2
-
MSG 1
R/W
R
for timing description and
1
9
1
-
-
MSG 0
R/W
R
0
8
0
-
-
CANSTML
CANMSG
7679H–CAN–08/08
page
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