AT90CAN128-16AI Atmel, AT90CAN128-16AI Datasheet - Page 134

• Manufacturer Part Number: AT90CAN128-16AI
• Description: IC MCU AVR FLASH 128K 64TQFP
• Manufacturer: Atmel
• Series: AVR® 90CANr

Specifications of AT90CAN128-16AI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: CAN, EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• For Use With: ATDVK90CAN1 - KIT DEV FOR AT90CAN128 MCU
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

13.10 Timer/Counter Timing Diagrams
134
AT90CAN32/64/128
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCRnx Register represents special cases when generating a PWM
waveform output in the phase correct PWM mode. If the OCRnx is set equal to BOTTOM the
output will be continuously low and if set equal to TOP the output will be set to high for non-
inverted PWM mode. For inverted PWM the output will have the opposite logic values.
The Timer/Counter is a synchronous design and the timer clock (clk
clock enable signal in the following figures. The figures include information on when interrupt
flags are set, and when the OCRnx Register is updated with the OCRnx buffer value (only for
modes utilizing double buffering).
Figure 13-10. Timer/Counter Timing Diagram, Setting of OCFnx, no Prescaling
Figure 13-11
Figure 13-11. Timer/Counter Timing Diagram, Setting of OCFnx, with Prescaler (f
Figure 13-12
frequency correct PWM mode the OCRnx Register is updated at BOTTOM. The timing diagrams
will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on.
The same renaming applies for modes that set the TOVn flag at BOTTOM.
shows the same timing data, but with the prescaler enabled.
shows the count sequence close to TOP in various modes. When using phase and
TCNTn
OCRnx
OCFnx
(clk
TCNTn
OCRnx
OCFnx
(clk
clk
clk
clk
clk
I/O
I/O
I/O
Tn
I/O
Tn
/1)
/8)
OCRnx - 1
OCRnx - 1
Figure 13-10
OCRnx
OCRnx
shows a timing diagram for the setting of OCFnx.
OCRnx Value
OCRnx Value
OCRnx + 1
OCRnx + 1
Tn
) is therefore shown as a
OCRnx + 2
OCRnx + 2
clk_I/O
7679H–CAN–08/08
/8)