AT90CAN128-16AI Atmel, AT90CAN128-16AI Datasheet - Page 15
![IC MCU AVR FLASH 128K 64TQFP](/photos/12/13/121332/313-64-tqfp_sml.jpg)
AT90CAN128-16AI
Manufacturer Part Number
AT90CAN128-16AI
Description
IC MCU AVR FLASH 128K 64TQFP
Manufacturer
Atmel
Series
AVR® 90CANr
Specifications of AT90CAN128-16AI
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
CAN, EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
For Use With
ATDVK90CAN1 - KIT DEV FOR AT90CAN128 MCU
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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3.8
3.8.1
7679H–CAN–08/08
Reset and Interrupt Handling
Interrupt Behavior
Figure 3-6
operation using two register operands is executed, and the result is stored back to the destina-
tion register.
Figure 3-6.
The AVR provides several different interrupt sources. These interrupts and the separate Reset
Vector each have a separate program vector in the program memory space. All interrupts are
assigned individual enable bits which must be written logic one together with the Global Interrupt
Enable bit in the Status Register in order to enable the interrupt. Depending on the Program
Counter value, interrupts may be automatically disabled when Boot Lock bits BLB02 or BLB12
are programmed. This feature improves software security. See the section
ming” on page 336
The lowest addresses in the program memory space are by default defined as the Reset and
Interrupt Vectors. The complete list of vectors is shown in
determines the priority levels of the different interrupts. The lower the address the higher is the
priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request
0. The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the IVSEL
bit in the MCU Control Register (MCUCR). Refer to
The Reset Vector can also be moved to the start of the Boot Flash section by programming the
BOOTRST Fuse, see
321.
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are dis-
abled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled
interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a
Return from Interrupt instruction – RETI – is executed.
There are basically two types of interrupts. The first type is triggered by an event that sets the
interrupt flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector
in order to execute the interrupt handling routine, and hardware clears the corresponding inter-
rupt flag. Interrupt flags can also be cleared by writing a logic one to the flag bit position(s) to be
cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared,
the interrupt flag will be set and remembered until the interrupt is enabled, or the flag is cleared
by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable
bit is cleared, the corresponding interrupt flag(s) will be set and remembered until the Global
Interrupt Enable bit is set, and will then be executed by order of priority.
Register Operands Fetch
ALU Operation Execute
shows the internal timing concept for the Register File. In a single clock cycle an ALU
Total Execution T i me
Result Write Back
Single Cycle ALU Operation
for details.
“Boot Loader Support – Read-While-Write Self-Programming” on page
clk
CPU
T1
“Interrupts” on page 60
T2
“Interrupts” on page
AT90CAN32/64/128
T3
for more information.
“Memory Program-
60. The list also
T4
15
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