AT90CAN128-16AI Atmel, AT90CAN128-16AI Datasheet - Page 241
![IC MCU AVR FLASH 128K 64TQFP](/photos/12/13/121332/313-64-tqfp_sml.jpg)
AT90CAN128-16AI
Manufacturer Part Number
AT90CAN128-16AI
Description
IC MCU AVR FLASH 128K 64TQFP
Manufacturer
Atmel
Series
AVR® 90CANr
Specifications of AT90CAN128-16AI
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
CAN, EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
For Use With
ATDVK90CAN1 - KIT DEV FOR AT90CAN128 MCU
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT90CAN128-16AI
Manufacturer:
ALTERA
Quantity:
101
Company:
Part Number:
AT90CAN128-16AI
Manufacturer:
ATMEL
Quantity:
642
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19.4
19.4.1
19.4.2
7679H–CAN–08/08
CAN Channel
Configuration
Bit Timing
The CAN channel can be in:
Figure 19-6. Listening Mode
FSM’s (Finite State Machine) of the CAN channel need to be synchronous to the time quantum.
So, the input clock for bit timing is the clock used into CAN channel FSM’s.
Field and segment abbreviations:
• Enabled mode
• Standby mode
• Listening mode
• BRP: Baud Rate Prescaler.
• TQ: Time Quantum (output of Baud Rate Prescaler).
• SYNS: SYNchronization Segment is 1 TQ long.
• PRS: PRopagation time Segment is programmable to be 1, 2, ..., 8 TQ long.
• PHS1: PHase Segment 1 is programmable to be 1, 2, ..., 8 TQ long.
• PHS2: PHase Segment 2 is programmable to be ≤ PHS1 and ≥ INFORMATION
• INFORMATION PROCESSING TIME is 2 TQ.
• SJW: (Re) Synchronization Jump Width is programmable between 1 and min(4, PHS1).
PROCESSING TIME.
– the CAN channel (internal TxCAN & RxCAN) is enabled,
– the input clock is enabled.
– the transmitter constantly provides a recessive level (on internal TxCAN) and the
– input clock is enabled,
– the registers and pages remain accessible.
– enables a hardware loop back, internal TxCAN on internal RxCAN
– provides a recessive level on TXCAN output pin
– does not disable RXCAN input pin
– freezes TEC and REC error counters
In this mode:
In standby mode:
This mode is transparent for the CAN channel:
receiver is disabled,
LISTEN
RxCAN
TxCAN
internal
internal
1
0
PD5
PD6
AT90CAN32/64/128
RXCAN
TXCAN
241
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