ATMEGA323L-4AI Atmel, ATMEGA323L-4AI Datasheet - Page 96

• Manufacturer Part Number: ATMEGA323L-4AI
• Description: IC AVR MCU 32K LV 4MZ IND 44TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA323L-4AI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: ATMEGA323L4AI

USART Control and Status
Register B – UCSRB
96
ATmega323(L)
• Bit 7 – RXCIE: RX Complete Interrupt Enable
Setting this bit to one enables interrupt on the RXC Flag. A USART Receive Complete
interrupt will be generated only if the RXCIE bit is set, the Global Interrupt Flag in SREG
is set and the RXC bit in UCSRA is set.
• Bit 6 – TXCIE: TX Complete Interrupt Enable
Setting this bit to one enables interrupt on the TXC Flag. A USART Transmit Complete
interrupt will be generated only if the TXCIE bit is set, the Global Interrupt Flag in SREG
is set and the TXC bit in UCSRA is set.
• Bit 5 – UDRIE: USART Data Register Empty Interrupt Enable
Setting this bit to one enables interrupt on the UDRE Flag. A Data Register Empty Inter-
rupt will be generated only if the UDRIE bit is set, the Global Interrupt Flag in SREG is
set and the UDRE bit in UCSRA is set.
• Bit 4 – RXEN: Receiver Enable
Setting this bit to one enables the USART Receiver. The Receiver will override normal
port operation for the RxD pin when enabled. Disabling the Receiver will flush the
Receive Buffer invalidating the FE, DOR, and PE Flags.
• Bit 3 – TXEN: Transmitter Enable
Setting this bit to one enables the USART Transmitter. The Transmitter will override nor-
mal port operation for the TxD pin when enabled. The disabling of the Transmitter
(setting the TXEN to zero) will not become effective until ongoing and pending transmis-
sions are completed, i.e. when the Transmit Shift Register and Transmit Buffer Register
does not contain data to be transmitted. When disabled the Transmitter will no longer
override the TxD port.
• Bit 2 – UCSZ2: Character Size
The UCSZ2 bits combined with the UCSZ1:0 bit in UCSRC sets the number of data bits
(character size) in a frame the Receiver and Transmitter use.
• Bit 1 – RXB8: Receive Data Bit 8
RXB8 is the ninth data bit of the received character when operating with serial frames
with nine data bits. Must be read before reading the low bits from UDR.
• Bit 0 – TXB8: Transmit Data Bit 8
TXB8 is the ninth data bit in the character to be transmitted when operating with serial
frames with nine data bits. Must be written before writing the low bits to UDR.
Bit
$0A ($2A)
Read/Write
Initial Value
RXCIE
R/W
7
0
TXCIE
R/W
6
0
UDRIE
R/W
5
0
RXEN
R/W
4
0
TXEN
R/W
3
0
UCSZ2
R/W
2
0
RXB8
R
1
0
TXB8
1457G–AVR–09/03
W
0
0
UCSRB