ATMEGA323L-4AI Atmel, ATMEGA323L-4AI Datasheet - Page 54

• Manufacturer Part Number: ATMEGA323L-4AI
• Description: IC AVR MCU 32K LV 4MZ IND 44TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA323L-4AI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: ATMEGA323L4AI

16-bit Timer/Counter1
54
ATmega323(L)
Power-up Reset or wake-up from Power-down or Standby mode, the user should be
aware of the fact that this Oscillator might take as long as one second to stabilize. The
user is advised to wait for at least one second before using Timer/Counter2 after Power-
up or wake-up from Power-down or Standby mode. The contents of all Timer/Counter2
Registers must be considered lost after a wake-up from Power-down or Standby mode
due to unstable clock signal upon start-up, no matter whether the Oscillator is in use or a
clock signal is applied to the TOSC1 pin.
Description of wake up from Power-save or Extended Standby mode when the timer is
clocked asynchronously: When the interrupt condition is met, the wake up process is
started on the following cycle of the timer clock, that is, the timer is always advanced by
at least one before the processor can read the counter value. After wake-up, the MCU is
halted for four cycles, it executes the interrupt routine, and resumes execution from the
instruction following SLEEP.
During asynchronous operation, the synchronization of the Interrupt Flags for the asyn-
chronous timer takes three processor cycles plus one timer cycle. The timer is therefore
advanced by at least one before the processor can read the timer value causing the set-
ting of the Interrupt Flag. The Output Compare Pin is changed on the timer clock and is
not synchronized to the processor clock.
Figure 36 shows the block diagram for Timer/Counter1.
Figure 36. Timer/Counter1 Block Diagram
The 16-bit Timer/Counter1 can select clock source from CK, prescaled CK, or an exter-
nal pin. In addition it can be stopped as described in section “Timer/Counter1 Control
15
15
15
15
REGISTER (TIMSK)
TIMER/COUNTER1 OUTPUT COMPARE REGISTER A
TIMER INT. MASK
T/C1 INPUT CAPTURE REGISTER (ICR1)
T/C1 OVER-
FLOW IRQ
TIMER/COUNTER1 (TCNT1)
16 BIT COMPARATOR
8
8
8
8
T/C1 COMPARE
7
7
7
7
MATCH A IRQ
REGISTER (TIFR)
TIMER INT. FLAG
CAPTURE
TRIGGER
T/C1 COMPARE
MATCH B IRQ
0
0
0
0
REGISTER A (TCCR1A)
15
15
TIMER/COUNTER1 OUTPUT COMPARE REGISTER B
T/C CLEAR
T/C CLOCK SOURCE
UP/DOWN
CAPTURE IRQ
T/C1 CONTROL
T/C1 INPUT
16 BIT COMPARATOR
CONTROL
8
8
LOGIC
7
7
REGISTER B (TCCR1B)
T/C1 CONTROL
1457G–AVR–09/03
0
0
PSR10
CK
T1