ATMEGA323L-4AI Atmel, ATMEGA323L-4AI Datasheet - Page 240

• Manufacturer Part Number: ATMEGA323L-4AI
• Description: IC AVR MCU 32K LV 4MZ IND 44TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA323L-4AI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: ATMEGA323L4AI

240
ATmega323(L)
3. TWI is Speed Limited in Slave Mode
2. Problems with UBRR Settings
1. Missing OverRun Flag and Fake Frame Error in USART
The following is not errata for ATmega323, all revisions. However, a proposal for solving
problems regarding the JTAG instruction IDCODE is presented below.
When the Two-wire Serial Interface operates in Slave mode, frames may be unde-
tected if the CPU frequency is less than 64 times the bus frequency.
Problem Fix/Workaround
Ensure that the CPU frequency is at least 64 times the TWI bus frequency.
The baud rate corresponding to the previous UBRR setting is used for the first trans-
mitted/received bit when either UBRRH or UBRRL is written. This will disturb
communication if the UBRR is changed from a very high to a very low baud rate set-
ting, as the internal baud rate counter will have to count down to zero before using
the new setting.
In addition, writing to UBRRL incorrectly clears the UBRRH setting.
Problem Fix/Workaround
UBRRH must be written after UBRRL because setting UBRRL clears UBRRH. By
doing an additional dummy write to UBRRH, the baud rate is set correctly. The fol-
lowing is an example on how to set UBRR. UBRRH is updated first for upward
compatibility with corrected devices.
ldi r17, HIGH(baud)
ldi r16, LOW(baud)
out UBRRH, r17
out UBRRL, r16
out UBRRH, r17
out UBRRH, r17
When the USART has received three characters without any of them been read, the
USART FIFO is full. If the USART detects the start bit of a fourth character, the Data
OverRun (DOR) Flag will be set for the third character. However, if a read from the
USART Data Register is performed just after the start bit of the fourth byte is
received, a Frame Error is generated for character three. If the USART Data Regis-
ter is read between the reception of the first data bit and the end of the fourth
character, the Data OverRun Flag of character three will be lost.
Problem Fix/Workaround
The user should design the application to never completely fill the USART FIFO. If
this is not possible, the user must use a high-level protocol to be able to detect if any
characters were lost and request a retransmission if this happens.
IDCODE masks data from TDI input
The public but optional JTAG instruction IDCODE is not implemented correctly
according to IEEE1149.1; a logic one is scanned into the shift register instead of the
TDI input while shifting the Device ID Register. Hence, captured data from the pre-
ceding devices in the boundary scan chain are lost and replaced by all-ones, and
data to succeeding devices are replaced by all-ones during Update-DR.
If ATmega323 is the only device in the scan chain, the problem is not visible.
; Added for upward compatibility
; Set new UBRRL, UBRRH incorrectly cleared
; Set new UBRRH
; Loads the baud rate counter with new (correct) value
1457G–AVR–09/03