ATMEGA323L-4AI Atmel, ATMEGA323L-4AI Datasheet - Page 78

• Manufacturer Part Number: ATMEGA323L-4AI
• Description: IC AVR MCU 32K LV 4MZ IND 44TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA323L-4AI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: ATMEGA323L4AI

Frame Formats
78
ATmega323(L)
Figure 47. Synchronous Mode XCK Timing
The UCPOL bit UCRSC selects which XCK clock edge is used for data sampling and
which is used for data change. As Figure 47 shows, when UCPOL is zero the data will
be changed at falling XCK edge and sampled at rising XCK edge. If UCPOL is set, the
data will be changed at rising XCK edge and sampled at falling XCK edge.
A serial frame is defined to be one character of data bits with synchronization bits (start
and stop bits), and optionally a parity bit for error checking. The USART accept all 30
combinations of the following as valid frame formats:
•
•
•
•
A frame starts with the start bit followed by the least significant data bit. Then the next
data bits, up to a total of nine, are succeeding, ending with the most significant bit. If
enabled, the parity bit is inserted after the data bits, before the stop bits. When a com-
plete frame is transmitted, it can be directly followed by a new frame, or the
communication line can be set to a idle (high) state. Figure 48 illustrates the possible
combinations of the frame formats. Bits inside brackets are optional.
Figure 48. Frame Formats
St
(n)
P
Sp
IDLE
UCPOL = 0
UCPOL = 1
1 start bit
5, 6, 7, 8, or 9 data bits
no, even, or odd parity bit
1 or 2 stop bits
(IDLE)
Start bit, always low.
Data bits (0 to 8).
Parity bit. Can be odd or even.
Stop bit, always high.
No transfers on the communication line (RxD or TxD).
An IDLE line must be high.
RxD / TxD
RxD / TxD
St
XCK
XCK
0
1
2
3
4
FRAME
[5]
[6]
[7]
[8]
[P]
Sample
Sample
Sp1 [Sp2]
(St / IDLE)
1457G–AVR–09/03