ATMEGA323L-4AI Atmel, ATMEGA323L-4AI Datasheet - Page 36

• Manufacturer Part Number: ATMEGA323L-4AI
• Description: IC AVR MCU 32K LV 4MZ IND 44TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA323L-4AI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: ATMEGA323L4AI

The Timer/Counter Interrupt
Flag Register – TIFR
36
ATmega323(L)
• Bit 7 – OCF2: Output Compare Flag 2
The OCF2 bit is set (one) when a Compare Match occurs between the Timer/Counter2
and the data in OCR2 – Output Compare Register2. OCF2 is cleared by hardware when
executing the corresponding interrupt handling vector. Alternatively, OCF2 is cleared by
writing a logic one to the flag. When the I-bit in SREG, and OCIE2 (Timer/Counter2
Compare match Interrupt Enable), and the OCF2 are set (one), the Timer/Counter2
Compare match Interrupt is executed.
• Bit 6 – TOV2: Timer/Counter2 Overflow Flag
The TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared
by hardware when executing the corresponding interrupt handling vector. Alternatively,
TOV2 is cleared by writing a logic one to the flag. When the SREG I-bit, and TOIE2
(Tim er /Counter2 Overf low Interrupt Enabl e), and TO V2 are set (one), the
Timer/Counter2 Overflow interrupt is executed. In PWM mode, this bit is set when
Timer/Counter2 changes counting direction at $00.
• Bit 5 – ICF1: Input Capture Flag 1
The ICF1 bit is set (one) to flag an Input Capture event, indicating that the
Timer/Counter1 value has been transferred to the Input Capture Register – ICR1. ICF1
is cleared by hardware when executing the corresponding interrupt handling vector.
Alternatively, ICF1 is cleared by writing a logic one to the flag. When the I-bit in SREG,
and TICIE1 (Timer/Counter1 Input Capture Interrupt Enable), and the ICF1 are set
(one), the Timer/Counter1 Capture Interrupt is executed.
• Bit 4 – OCF1A: Output Compare Flag 1A
The OCF1A bit is set (one) when a Compare Match occurs between the Timer/Counter1
and the data in OCR1A – Output Compare Register 1A. OCF1A is cleared by hardware
when executing the corresponding interrupt handling vector. Alternatively, OCF1A is
cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1A
(Timer/Counter1 Compare Match Interrupt A Enable), and the OCF1A are set (one), the
Timer/Counter1 Compare Match A Interrupt is executed.
• Bit 3 – OCF1B: Output Compare Flag 1B
The OCF1B bit is set (one) when a Compare Match occurs between the Timer/Counter1
and the data in OCR1B – Output Compare Register 1B. OCF1B is cleared by hardware
when executing the corresponding interrupt handling vector. Alternatively, OCF1B is
cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1B
(Timer/Counter1 Compare Match Interrupt B Enable), and the OCF1B are set (one), the
Timer/Counter1 Compare Match B Interrupt is executed.
Bit
$38 ($58)
Read/Write
Initial Value
OCF2
R/W
7
0
TOV2
R/W
6
0
ICF1
R/W
5
0
OCF1A
R/W
4
0
OCF1B
R/W
3
0
TOV1
R/W
2
0
OCF0
R/W
1
0
TOV0
R/W
1457G–AVR–09/03
0
0
TIFR