ATMEGA323L-4AI Atmel, ATMEGA323L-4AI Datasheet - Page 158

• Manufacturer Part Number: ATMEGA323L-4AI
• Description: IC AVR MCU 32K LV 4MZ IND 44TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA323L-4AI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: ATMEGA323L4AI

The Test Access Port –
TAP
158
ATmega323(L)
The JTAG interface is accessed through four of the AVR’s pins. In JTAG terminology,
these pins constitute the Test Access Port – TAP. These pins are
•
•
•
•
The IEEE std. 1149.1 also specifies an optional TAP signal; TRST – Test ReSeT –
which is not provided.
When the JTAGEN fuse is unprogrammed, these four TAP pins are normal port pins
and the TAP controller is in reset. When programmed and the JTD bit in MCUCSR is
cleared, the TAP input signals are internally pulled high and the JTAG is enabled for
Boundary-scan and programming. In this case, the TAP output pin (TDO) is left floating
in states where the JTAG TAP controller is not shifting data, and must therefore be con-
nected to a pull-up resistor or other hardware having pull-ups (for instance the TDI-input
of the next device in the scan chain). The device is shipped with this fuse programmed.
For the On-chip Debug system, in addition the RESET pin is monitored by the debugger
to be able to detect External Reset sources. The debugger can also pull the RESET pin
low to reset the whole system, assuming only open collectors on reset line are used in
the application.
TMS: Test mode select. This pin is used for navigating through the TAP-controller
state machine.
TCK: Test clock. JTAG operation is synchronous to TCK
TDI: Test Data In. Serial input data to be shifted in to the Instruction Register or Data
Register (Scan Chains)
TDO: Test Data Out. Serial output data from Instruction Register or Data Register
1457G–AVR–09/03