ATMEGA323L-4AI Atmel, ATMEGA323L-4AI Datasheet - Page 9

• Manufacturer Part Number: ATMEGA323L-4AI
• Description: IC AVR MCU 32K LV 4MZ IND 44TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA323L-4AI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: ATMEGA323L4AI

1457G–AVR–09/03
Figure 5. The ATmega323 AVR Enhanced RISC Architecture
The AVR uses a Harvard architecture concept – with separate memories and buses for
Program and Data. The Program memory is executed with a single level pipelining.
While one instruction is being executed, the next instruction is pre-fetched from the Pro-
gram memory. This concept enables instructions to be executed in every clock cycle.
The Program memory is In-System Reprogrammable Flash memory.
With the jump and call instructions, the whole 16K address space is directly accessed.
Most AVR instructions have a single 16-bit word format. Every Program memory
address contains a 16- or 32-bit instruction.
Program Flash memory space is divided in two sections, the Boot Program section (512
to 4K bytes, see page 177) and the Application Program section. Both sections have
dedicated Lock bits for write and read/write protection. The SPM instruction that writes
into the Application Flash memory section is allowed only in the Boot Program section.
During interrupts and subroutine calls, the return address Program Counter (PC) is
stored on the Stack. The Stack is effectively allocated in the general data SRAM, and
consequently the Stack size is only limited by the total SRAM size and the usage of the
SRAM. All user programs must initialize the SP in the Reset Routine (before subroutines
or interrupts are executed). The 12-bit Stack Pointer SP is read/write accessible in the
I/O space.
Control Lines
Instruction
Instruction
16K X 16
Program
Memory
Register
Decoder
Program
Counter
and Control
EEPROM
Registrers
I/O Lines
Purpose
General
1K x 8
SRAM
2K x 8
Data Bus 8-bit
Status
32 x 8
Data
ALU
32
ATmega323(L)
MUX and Gain
A/D Converter
Timer/Counter
Timer/Counter
Timer/Counter
Comparator
with PWM
with PWM
Watchdog
with PWM
Interrupt
TWI Bus
Serial
USART
Analog
16-bit
Timer
Serial
Unit
8-bit
Unit
8-bit
SPI
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