ATMEGA323L-4AI Atmel, ATMEGA323L-4AI Datasheet - Page 95

• Manufacturer Part Number: ATMEGA323L-4AI
• Description: IC AVR MCU 32K LV 4MZ IND 44TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA323L-4AI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: ATMEGA323L4AI

ATmega323(L)
• Bit 5 – UDRE: USART Data Register Empty
The UDRE Flag indicates if the transmit buffer (UDR) is ready to receive new data. If
UDRE is one the buffer is empty and therefore ready be written. The UDRE Flag can
generate a Data Register Empty interrupt (see description of the UDRIE bit).
UDRE is set (one) after a reset to indicate that the Transmitter is ready.
• Bit 4 – FE: Frame Error
This bit is set if the next character in the receive buffer had a Frame Error when
received. I.e. when the first stop bit of the next character in the receive buffer is zero.
This bit is valid until the receive buffer (UDR) is read. The FE bit is zero when the stop
bit of received data is one. Always set this bit to zero when writing to UCSRA.
• Bit 3 – DOR: Data OverRun
This bit is set if a Data OverRun condition is detected. A Data OverRun occur when the
receive buffer is full (two characters), it is a new character waiting in the Receive Shift
Register, and a new start bit is detected. Always set this bit to zero when writing to
UCSRA.
• Bit 2 – PE: Parity Error
This bit is set if the next character in the receive buffer had a Parity Error when received
and the parity checking was enabled at that point (UPM1 = 1). This bit is valid until the
Receive Buffer (UDR) is read. Always set this bit to zero when writing to UCSRA.
• Bit 1 – U2X: Double the USART Transmission Speed
Setting this bit only has effect for the asynchronous operation. Set this bit to zero when
using synchronous operation.
Setting this bit will reduce the divisor of the baud rate divider from 16 to 8 effectively
doubling the transfer rate for asynchronous communication.
• Bit 0 – MPCM: Multi-processor Communication Mode
Setting this bit enables the Multi-processor Communication mode. When the MPCM bit
is set, all the incoming frames received by the USART Receiver that do not contain
address information will be ignored. The Transmitter is unaffected by the MPCM setting.
For more detailed information see “Multi-processor Communication Mode” on page 91.
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