PIC16C745/JW Microchip Technology, PIC16C745/JW Datasheet - Page 20
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PIC16C745/JW
Manufacturer Part Number
PIC16C745/JW
Description
IC MCU EPROM8KX14 USB A/D 28CDIP
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16C745-ISP.pdf
(165 pages)
3.PIC16C745-ISP.pdf
(6 pages)
4.PIC16C745-ISP.pdf
(6 pages)
Specifications of PIC16C745/JW
Core Processor
PIC
Core Size
8-Bit
Speed
24MHz
Connectivity
SCI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
14KB (8K x 14)
Program Memory Type
EPROM, UV
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4.35 V ~ 5.25 V
Data Converters
A/D 5x8b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
28-CDIP (0.300", 7.62mm) Window
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16C745/JW
Manufacturer:
MICROCHIP
Quantity:
51
Part Number:
PIC16C745/JW
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
PIC16C745/765
TABLE 4-1:
DS41124C-page 20
Address
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch-
18Fh
190h
191h
192h
193h
194h
195h
196h
197h
198h
199h
19Ah
19Bh-
19Fh
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as ’0’.
Note 1:
Bank 3
2: Other (non power-up) RESETS include external RESET through MCLR and Watchdog Timer Reset.
3: These registers can be addressed from any bank.
4: The Parallel Slave Port (PORTD and PORTE) is not implemented on the PIC16C745, always maintain these bits clear.
OPTION_REG
INDF
PCL
STATUS
FSR
TRISB
PCLATH
INTCON
UIR
UIE
UEIR
UEIE
USTAT
UCTRL
UADDR
USWSTAT
UEP0
UEP1
UEP2
Reserved
Shaded locations are unimplemented, read as ‘0’.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents
are transferred to the upper byte of the program counter.
Name
(3)
(3)
(3)
—
—
—
—
—
(3)
(1,3)
(3)
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Addressing this location uses contents of FSR to address data memory (not a physical register)
Program Counter’s (PC) Least Significant Byte
Indirect data memory address pointer
Unimplemented
PORTB Data Direction Register
Unimplemented
Unimplemented
Unimplemented
Unimplemented
BTS_ERR OWN_ERR WRT_ERR
BTS_ERR OWN_ERR WRT_ERR
Reserved, do not use.
SWSTAT7 SWSTAT6
RBPU
Bit 7
IRP
GIE
—
—
—
—
—
—
—
—
—
INTEDG
ADDR6
PEIE
Bit 6
RP1
—
—
—
—
—
—
—
—
SWSTAT5
ADDR5
STALL
STALL
T0CS
Bit 5
T0IE
SEO
RP0
—
—
—
—
—
Write Buffer for the upper 5 bits of the Program Counter
BTO_ERR
BTO_ERR
SWSTAT4
PKT_DIS
Preliminary
ENDP1
ADDR4
UIDLE
UIDLE
T0SE
INTE
Bit 4
TO
—
—
—
EP_CTL_DIS EP_OUT_EN EP_IN_EN EP_STALL ---- 0000 ---- 0000
EP_CTL_DIS EP_OUT_EN EP_IN_EN EP_STALL ---- 0000 ---- 0000
EP_CTL_DIS EP_OUT_EN EP_IN_EN EP_STALL ---- 0000 ---- 0000
TOK_DNE
TOK_DNE
SWSTAT3
DEV_ATT
ENDP0
ADDR3
DFN8
DFN8
RBIE
Bit 3
PSA
PD
SWSTAT2
ACTIVITY
ACTIVITY
RESUME
ADDR2
CRC16
CRC16
Bit 2
PS2
T0IF
IN
Z
SWSTAT1 SWSTAT0 0000 0000 0000 0000
SUSPND
ADDR1
UERR
UERR
CRC5
CRC5
Bit 1
INTF
PS1
DC
—
2000 Microchip Technology Inc.
USB_RST --00 0000 --00 0000
USB_RST --00 0000 --00 0000
PID_ERR 0000 0000 0000 0000
PID_ERR 0000 0000 0000 0000
ADDR0
Bit 0
RBIF
PS0
—
—
C
0000 0000 0000 0000
1111 1111 1111 1111
0000 0000 0000 0000
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
1111 1111 1111 1111
---0 0000 ---0 0000
0000 000x 0000 000u
---x xx-- ---u uu--
--x0 000- --xq qqq-
-000 0000 -000 0000
0000 0000 0000 0000
Value on:
POR,
BOR
—
—
—
—
—
other resets
Value on all
(2)
—
—
—
—
—