PIC16C745/JW Microchip Technology, PIC16C745/JW Datasheet - Page 101
![IC MCU EPROM8KX14 USB A/D 28CDIP](/photos/7/29/72984/150-28-cdip_sml.jpg)
PIC16C745/JW
Manufacturer Part Number
PIC16C745/JW
Description
IC MCU EPROM8KX14 USB A/D 28CDIP
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16C745-ISP.pdf
(165 pages)
3.PIC16C745-ISP.pdf
(6 pages)
4.PIC16C745-ISP.pdf
(6 pages)
Specifications of PIC16C745/JW
Core Processor
PIC
Core Size
8-Bit
Speed
24MHz
Connectivity
SCI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
14KB (8K x 14)
Program Memory Type
EPROM, UV
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4.35 V ~ 5.25 V
Data Converters
A/D 5x8b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
28-CDIP (0.300", 7.62mm) Window
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16C745/JW
Manufacturer:
MICROCHIP
Quantity:
51
Part Number:
PIC16C745/JW
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
13.2.5
In EC mode, users may directly drive the PIC16C745/
765 provided that this external clock source meets the
AC/DC timing requirements listed in Section 17.4.
Figure 13-2 below shows how an external clock circuit
should be configured.
FIGURE 13-2: EXTERNAL CLOCK INPUT
FIGURE 13-3: OSCILLATOR/PLL CLOCK CONTROL
13.3
The PIC16CXX differentiates between various kinds of
RESET:
• Power-on Reset (POR)
• MCLR Reset during normal operation
• MCLR Reset during SLEEP
• WDT Reset (normal operation)
• Brown-out Reset (BOR)
Some registers are not affected in any RESET condi-
tion; their status is unknown on POR and unchanged in
any other RESET. Most other registers are reset to a
“RESET state” on POR, on the MCLR and WDT Reset,
on MCLR Reset during SLEEP, and on BOR. The TO
and PD bits are set or cleared differently in different
RESET situations as indicated in Table 13-4. These
bits are used in software to determine the nature of the
RESET. See Table 13-7 for a full description of RESET
states of all registers.
OSC2
OSC1
2000 Microchip Technology Inc.
Clock from
ext. system
CLKOUT
EXTERNAL CLOCK IN
RESET
OPERATION (EC OSC
CONFIGURATION)
EC
E4
HS
H4
OSC1
OSC2/CLKOUT
PIC16C745/765
4x PLL
Preliminary
EC
E4
HS
H4
13.2.6
In E4 mode, a PLL module is switched on in-line with
the clock provided to OSC1. The output of the PLL
drives F
A simplified block diagram of the on-chip RESET circuit
is shown in Figure 13-4.
The PICmicro
MCLR Reset path. The filter will detect and ignore
small pulses.
It should be noted that a WDT Reset does not drive
MCLR pin low.
Note: CLKOUT is the same frequency as OSC1 if
24 MHz
F
INT
INT
E4 MODE
in E4 mode, otherwise CLKOUT = OSC1/4.
.
®
6 MHz
PIC16C745/765
devices have a MCLR noise filter in the
Generator
Q Clock
DS41124C-page 101
To Circuits