SAK-TC1767-256F80HL AD Infineon Technologies, SAK-TC1767-256F80HL AD Datasheet - Page 25

• Manufacturer Part Number: SAK-TC1767-256F80HL AD
• Description: IC MCU 32BIT FLASH 176-LQFP
• Manufacturer: Infineon Technologies
• Series: TC17xxr

Specifications of SAK-TC1767-256F80HL AD

• Core Processor: TriCore
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: ASC, CAN, MLI, MSC, SSC
• Peripherals: DMA, POR, WDT
• Number Of I /o: 88
• Program Memory Size: 2MB (2M x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.42 V ~ 1.58 V
• Data Converters: A/D 4x10b, 32x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 176-LFQFP
• Data Bus Width: 32 bit
• Data Ram Size: 92 KB
• Interface Type: SPI
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 88
• Number Of Timers: 2
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (12 bit, 16 Channel)
• Packages: PG-LQFP-176
• Max Clock Frequency: 80.0 MHz
• Sram (incl. Cache): 128.0 KByte
• Can Nodes: 2
• A / D Input Lines (incl. Fadc): 36
• Program Memory: 2.0 MB
• For Use With: B158-H8539-G2-X-7600IN - KIT STARTER TC176X SERIES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: SP000442086

2.3.4
The following SCU introduction gives an overview about the TC1767 System Control
Unit (SCU).
2.3.4.1
The Clock Generation Unit (CGU) allows a very flexible clock generation for the TC1767.
During user program execution the frequency can be programmed for an optimal ratio
between performance and power consumption.
2.3.4.2
The main features of the WDT are summarized here.
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2.3.4.3
The following reset request triggers are available:
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Note: The JTAG and OCDS resets are described in the OCDS chapter.
There are two basic types of reset request triggers:
Data Sheet
16-bit Watchdog counter
Selectable input frequency:
16-bit user-definable reload value for normal Watchdog operation, fixed reload value
for Time-Out and Prewarning Modes
Incorporation of the ENDINIT bit and monitoring of its modifications
Sophisticated Password Access mechanism with fixed and user-definable password
fields
Access Error Detection: Invalid password (during first access) or invalid guard bits
(during second access) trigger the Watchdog reset generation
Overflow Error Detection: An overflow of the counter triggers the Watchdog reset
generation
Watchdog function can be disabled; access protection and ENDINIT monitor function
remain enabled
Double Reset Detection: If a Watchdog induced reset occurs twice, a severe system
malfunction is assumed and the TC1767 is held in reset until a system / class 0 reset
occurs.
1 External power-on hardware reset request trigger; PORST, (cold reset)
2 External System Request reset triggers; ESR0 and ESR1 (warm reset)
Watchdog Timer (WDT) reset request trigger, (warm reset)
Software reset (SW), (warm reset)
Debug (OCDS) reset request trigger, (warm reset)
JTAG reset (special reset)
Resets via the JTAG interface
System Control Unit
Clock Generation Unit
Features of the Watchdog Timer
Reset Operation
f
FPI
/256 or
f
21
FPI
/16384
Introduction
V1.3, 2009-09
TC1767