SAK-TC1767-256F80HL AD Infineon Technologies, SAK-TC1767-256F80HL AD Datasheet - Page 119

• Manufacturer Part Number: SAK-TC1767-256F80HL AD
• Description: IC MCU 32BIT FLASH 176-LQFP
• Manufacturer: Infineon Technologies
• Series: TC17xxr

Specifications of SAK-TC1767-256F80HL AD

• Core Processor: TriCore
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: ASC, CAN, MLI, MSC, SSC
• Peripherals: DMA, POR, WDT
• Number Of I /o: 88
• Program Memory Size: 2MB (2M x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.42 V ~ 1.58 V
• Data Converters: A/D 4x10b, 32x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 176-LFQFP
• Data Bus Width: 32 bit
• Data Ram Size: 92 KB
• Interface Type: SPI
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 88
• Number Of Timers: 2
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (12 bit, 16 Channel)
• Packages: PG-LQFP-176
• Max Clock Frequency: 80.0 MHz
• Sram (incl. Cache): 128.0 KByte
• Can Nodes: 2
• A / D Input Lines (incl. Fadc): 36
• Program Memory: 2.0 MB
• For Use With: B158-H8539-G2-X-7600IN - KIT STARTER TC176X SERIES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: SP000442086

7) The RCLK max. input rise/fall times are best case parameters for
5.3.8.2
Table 24
Parameter
FCLP clock period
SOP/ENx outputs delay
from FCLP rising edge
SDI bit time
SDI rise time
SDI fall time
1) FCLP signal rise/fall times are the same as the A2 Pads rise/fall times.
2) FCLP signal high and low can be minimum 1 ×
3)
Figure 33
Note: Sample the data at SOP with the falling edge of FCLP in the target device.
Data Sheet
input signal rise/fall times can be used for longer RCLK clock periods.
T
MSCmin
FCLP
SOP
EN
SDI
=
T
Micro Second Channel (MSC) Interface Timing
SYS
MSC Interface Timing (Operating Conditions apply), C
MSC Interface Timing
= 1/
f
SYS
1)2)
. When
t
45
f
SYS
= 80 MHz,
Symbol
t
t
t
t
t
40
45
46
48
49
t
46
CC 2 ×
CC -10
CC 8 ×
SR
SR
t
40
t
40
T
Min.
MSC
= 25 ns
115
.
T
T
t
48
MSC
MSC
3)
t
Values
45
t
Typ.
–
46
f
SYS
= 80 MHz. For reduction of EMI, slower
Max.
–
10
–
100
100
t
Electrical Parameters
49
MSC_Tmg_1.vsd
Unit
ns
ns
ns
ns
ns
L
0.9
0.1
= 50 pF
0.9
0.1
V
V
V
V
V1.3, 2009-09
DDP
DDP
DDP
DDP
Note /
Test Con
dition
–
–
–
–
–
TC1767