SAK-TC1767-256F80HL AD Infineon Technologies, SAK-TC1767-256F80HL AD Datasheet - Page 111

• Manufacturer Part Number: SAK-TC1767-256F80HL AD
• Description: IC MCU 32BIT FLASH 176-LQFP
• Manufacturer: Infineon Technologies
• Series: TC17xxr

Specifications of SAK-TC1767-256F80HL AD

• Core Processor: TriCore
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: ASC, CAN, MLI, MSC, SSC
• Peripherals: DMA, POR, WDT
• Number Of I /o: 88
• Program Memory Size: 2MB (2M x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.42 V ~ 1.58 V
• Data Converters: A/D 4x10b, 32x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 176-LFQFP
• Data Bus Width: 32 bit
• Data Ram Size: 92 KB
• Interface Type: SPI
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 88
• Number Of Timers: 2
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (12 bit, 16 Channel)
• Packages: PG-LQFP-176
• Max Clock Frequency: 80.0 MHz
• Sram (incl. Cache): 128.0 KByte
• Can Nodes: 2
• A / D Input Lines (incl. Fadc): 36
• Program Memory: 2.0 MB
• For Use With: B158-H8539-G2-X-7600IN - KIT STARTER TC176X SERIES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: SP000442086

With rising number
of
accumulated jitter remains at a constant value. Further, a lower LMB-Bus clock
frequency
Figure 26
Figure 26
Note: The specified PLL jitter values are valid if the capacitive load per output pin does
Note: The maximum peak-to-peak noise on the pad supply voltage, measured between
Data Sheet
m
that is defined by the K2-factor of the PLL. Beyond this value of
Dm
not exceed
applications with many pins with high loads, driver strengths and toggle rates the
specified jitter values could be exceeded.
V
V
frequencies above 300 KHz.
The maximum peak-to peak noise on the pad supply votage, measured between
V
V
frequencies above 300 KHz.
±10.0
DDOSC3
PP
DDOSC
PP
±4.0
±2.0
±0.0
±8.0
±7.0
±6.0
±1.0
ns
= 100 mV for noise frequencies below 300 KHz and
= 100 mV for noise frequencies below 300 KHz and
f
gives the jitter curves for several K2 /
LMB
0
Dm
m
K2
at pin 105 and
Approximated Maximum Accumulated PLL Jitter for Typical LMB-
Bus Clock Frequencies
f
LMB
at pin 106 and
results in a higher absolute maximum jitter value.
= Max. jitter
= Number of consecutive f
= K2-divider of PLL
= 40 MHz (K2 = 10)
C
m
L
20
of clock cycles the maximum jitter increases linearly up to a value
= 20 pF with the maximum driver and sharp edge. In case of
f
LMB
= 133 MHz (K2 = 6)
f
LMB
V
V
= 40 MHz (K2 = 20)
f
SSOSC
40
LMB
SSOSC
= 80 MHz (K2 = 10)
LMB
at pin 104, is limited to a peak-to-peak voltage of
f
LMB
at pin 104, is limited to a peak-to-peak voltage of
f
periods
= 80 MHz (K2 = 6)
LMB
60
107
f
LMB
80
combinations.
100
Electrical Parameters
V
V
PP
PP
TC1767_PLL_JITT_C
= 40 mV for noise
= 40 mV for noise
120
m
the maximum
V1.3, 2009-09
TC1767
o
m
o