SAK-TC1767-256F80HL AD Infineon Technologies, SAK-TC1767-256F80HL AD Datasheet - Page 110

• Manufacturer Part Number: SAK-TC1767-256F80HL AD
• Description: IC MCU 32BIT FLASH 176-LQFP
• Manufacturer: Infineon Technologies
• Series: TC17xxr

Specifications of SAK-TC1767-256F80HL AD

• Core Processor: TriCore
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: ASC, CAN, MLI, MSC, SSC
• Peripherals: DMA, POR, WDT
• Number Of I /o: 88
• Program Memory Size: 2MB (2M x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.42 V ~ 1.58 V
• Data Converters: A/D 4x10b, 32x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 176-LFQFP
• Data Bus Width: 32 bit
• Data Ram Size: 92 KB
• Interface Type: SPI
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 88
• Number Of Timers: 2
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (12 bit, 16 Channel)
• Packages: PG-LQFP-176
• Max Clock Frequency: 80.0 MHz
• Sram (incl. Cache): 128.0 KByte
• Can Nodes: 2
• A / D Input Lines (incl. Fadc): 36
• Program Memory: 2.0 MB
• For Use With: B158-H8539-G2-X-7600IN - KIT STARTER TC176X SERIES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: SP000442086

5.3.5
Note: All PLL characteristics defined on this and the next page are not subject to
Table 20
Parameter
Accumulated jitter
VCO frequency range
VCO input frequency range
PLL base frequency
PLL lock-in time
1) The CPU base frequency with which the application software starts after PORST is calculated by dividing the
Phase Locked Loop Operation
When PLL operation is enabled and configured, the PLL clock
Bus clock
adjusting its output frequency to correspond to the input frequency (from crystal or clock
source), resulting in an accumulated jitter that is limited. This means that the relative
deviation for periods of more than one clock cycle is lower than for a single clock cycle.
This is especially important for bus cycles using waitstates and for the operation of
timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train
generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter
is negligible.
Two formulas are defined for the (absolute) approximate maximum value of jitter
[ns] dependent on the K2 - factor, the LMB clock frequency
number
Data Sheet
limit values by 16 (this is the K2 factor after reset).
D
m ns
production test, but verified by design characterization.
[
m
]
f
of consecutive
LMB
Phase Locked Loop (PLL)
for
=
PLL Parameters (Operating Conditions apply)
) is constantly adjusted to the selected frequency. The PLL is constantly


-------------------------------------------- -
K2
×
else
1)
(
f
K2 100
LMB
740
≤
f
[
LMB
MHz
Symbol
|D
f
f
f
t
D
VCO
REF
PLLBASE
L
clock periods.
)
m ns
m
]
|
+
[
5


]
and
×
=


Min.
–
400
8
50
–
(
--------------------------------------------------------------- -
-------------------------------------------- -
K2
1 0 01
106
0 5 ,
–
×
(
,
×
f
m
LMB
f
740
LMB
≤
×
Values
(
Typ.
–
–
–
200
–
[
K2
f
MHz
LMB
[
MHz
)
×
[
]
MHz
(
m 1
+
320
] 1
Max.
7
800
16
200
–
5
–
f
VCO
]
f
Electrical Parameters
) 2 ⁄
LMB
)
+
(and with it the LMB-
)
0 01
in [MHz], and the
,
Unit Note /
ns
MHz –
MHz –
MHz –
µs
×
V1.3, 2009-09
K2
Test Con
dition
–
–


TC1767
D
m
(2)
(3)
in