SAK-TC1767-256F80HL AD Infineon Technologies, SAK-TC1767-256F80HL AD Datasheet - Page 113

• Manufacturer Part Number: SAK-TC1767-256F80HL AD
• Description: IC MCU 32BIT FLASH 176-LQFP
• Manufacturer: Infineon Technologies
• Series: TC17xxr

Specifications of SAK-TC1767-256F80HL AD

• Core Processor: TriCore
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: ASC, CAN, MLI, MSC, SSC
• Peripherals: DMA, POR, WDT
• Number Of I /o: 88
• Program Memory Size: 2MB (2M x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.42 V ~ 1.58 V
• Data Converters: A/D 4x10b, 32x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 176-LFQFP
• Data Bus Width: 32 bit
• Data Ram Size: 92 KB
• Interface Type: SPI
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 88
• Number Of Timers: 2
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (12 bit, 16 Channel)
• Packages: PG-LQFP-176
• Max Clock Frequency: 80.0 MHz
• Sram (incl. Cache): 128.0 KByte
• Can Nodes: 2
• A / D Input Lines (incl. Fadc): 36
• Program Memory: 2.0 MB
• For Use With: B158-H8539-G2-X-7600IN - KIT STARTER TC176X SERIES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: SP000442086

5.3.6
The following parameters are applicable for communication through the JTAG debug
interface. The JTAG module is fully compliant with IEEE1149.1-2000.
Note: These parameters are not subject to production test but verified by design and/or
Table 21
Parameter
TCK clock period
TCK high time
TCK low time
TCK clock rise time
TCK clock fall time
TDI/TMS setup
to TCK rising edge
TDI/TMS hold
after TCK rising edge
TDO valid after TCK falling
edge
TDO hold after TCK falling
edge
TDO high imped. to valid
from TCK falling edge
TDO valid to high imped.
from TCK falling edge
1) The falling edge on TCK is used to generate the TDO timing.
2) The setup time for TDO is given implicitly by the TCK cycle time.
Data Sheet
1)
1)
characterization.
(propagation delay)
JTAG Interface Timing
JTAG Interface Timing Parameters
(Operating Conditions apply)
1)2)
1)
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
5
6
7
8
8
18
9
10
SR
SR
SR
SR
SR
SR
SR
CC
CC
CC
CC
CC
Min.
25
12
10
–
–
6
6
–
–
2
–
–
109
Values
Typ.
–
–
–
–
–
–
–
–
–
–
–
–
Max.
–
–
–
4
4
–
–
13
3
–
14
13.5
Unit Note /
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Electrical Parameters
Test Condition
–
–
–
–
–
–
–
C
C
C
C
L
L
L
L
= 50 pF
= 20 pF
= 50 pF
= 50 pF
V1.3, 2009-09
TC1767