MAXQ3108-FFN+ Maxim Integrated Products, MAXQ3108-FFN+ Datasheet - Page 51

• Manufacturer Part Number: MAXQ3108-FFN+
• Description: IC MCU DUAL-CORE 16BIT 28-TSSOP
• Manufacturer: Maxim Integrated Products
• Series: MAXQ™r

Specifications of MAXQ3108-FFN+

• Core Processor: RISC
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 11K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-TSSOP
• Processor Series: MAXQ
• Core: RISC
• Data Bus Width: 16 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, JTAG, SPI
• Maximum Clock Frequency: 10 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 2
• Operating Supply Voltage: 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 5. Multipurpose Pin Description (continued)
All functional units in the MAXQ3108 are synchronized
to the system clock. The system clock can be generat-
ed from an internal oscillator with a 32,768Hz external
crystal/resonator or an internal FLL oscillator. The basic
unit of time in the MAXQ3108 is the system clock peri-
od. The UserCore receives a system clock that is one-
PIN
10
11
12
13
14
18
22
23
24
25
26
27
28
5
6
7
8
9
PRIMARY
P0.3
P0.4
P0.5
P2.5
P2.6
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P0.7
P0.6
P1.6
P2.4
P2.3
P2.2
P2.1
______________________________________________________________________________________
SECONDARY
MDIN0N
MDIN2N
MDIN1P
MDIN0P
Low-Power, Dual-Core Microcontroller
RXD1
SCLK
TXD1
SDA
TMS
TCK
TDO
TBB
TBA
SCL
CF1
CF2
RST
TDI
TERTIARY
INT10
CLKO
T2PB
MISO
SSEL
SQW
INT4
INT5
INT8
INT9
INT7
INT6
—
—
—
—
—
—
Clock
Do not enable outputs or clock gating on timer 2 when Manchester
decoder 1 is enabled. Also, do not enable INT3 when Manchester
decoder 1 is enabled or clock gating is used on timer 2.
Do not enable INT4 when the I
Do not enable INT5 when the I
Enabling pulse output 1 disables GPIO-port function on this port.
Enabling pulse output 2 disables GPIO-port function on this port.
When JTAG is in use, port pin 1.0 is unavailable. Do not enable INT8
when JTAG is active.
When JTAG is in use, port pin 1.1 is unavailable. Do not enable INT9
when JTAG is active.
When JTAG is in use, port pin 1.2 is unavailable. Do not enable INT10
when JTAG is active.
When JTAG is in use, port pin 1.3 and the SQW function are unavailable.
Do not enable INT11 when either JTAG or the SQW function is active.
When using TBB as an input, P1.4 must be configured as an input.
When using TBA as either an input or output, P1.5 must be configured as
an input.
Receive data function is only operational when the associated REN bit is
set is the SCON1 register. Do not enable an interrupt on this pin if it is
used for the serial receive function.
Transmit data is only presented to the pin when a character is actually
being transmitted. To use this pin as full-time transmit data, set the GPIO
port pin to output and load a 1 in the output register. Do not enable an
interrupt on this pin if it is used for the serial transmit function.
This is an active-low reset pin. Driving a low level on P1.6 causes the
MAXQ3108 to reset. The reset function on this pin can be disabled by
setting RSTD to 1.
When Manchester decoder 0 is enabled, set P2.4 as an input.
When using Manchester decoder 0, disable SPI and set P2.3 as an input.`
When CLKO (system clock for the CPU core) is enabled (that is, the
ECLKO bit is set), the SPI peripheral cannot be used.
When the Manchester decoder 2 is used, the SPI peripheral cannot be
used. The P2.1 port pin should be set to an input when using Manchester
decoder 2.
half the internal clock frequency. The Manchester
decoders, cubic sinc filters, and the DSPCore all
receive the undivided system clock.
The internal clock circuitry generates the system clock
from one of the two clock sources:
• Internal oscillator with a 32,768Hz external crystal or
resonator
2
2
C peripheral is in use.
C peripheral is in use.
COMMENT
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