MAXQ3108-FFN+ Maxim Integrated Products, MAXQ3108-FFN+ Datasheet - Page 24

IC MCU DUAL-CORE 16BIT 28-TSSOP

MAXQ3108-FFN+

Manufacturer Part Number
MAXQ3108-FFN+
Description
IC MCU DUAL-CORE 16BIT 28-TSSOP
Manufacturer
Maxim Integrated Products
Series
MAXQ™r
Datasheet

Specifications of MAXQ3108-FFN+

Core Processor
RISC
Core Size
16-Bit
Speed
10MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
21
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Ram Size
11K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
28-TSSOP
Processor Series
MAXQ
Core
RISC
Data Bus Width
16 bit
Data Ram Size
2 KB
Interface Type
I2C, JTAG, SPI
Maximum Clock Frequency
10 MHz
Number Of Programmable I/os
22
Number Of Timers
2
Operating Supply Voltage
3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Low-Power, Dual-Core Microcontroller
24
EIE1 (07h, 01h)
Initialization:
Read/Write Access:
EIE1.[3:0]: EX[11:8]
EIE1.[7:4]: Reserved
PD0 (08h, 01h)
Initialization:
Read/Write Access:
PD0.[7:0]:
PD1 (09h, 01h)
Initialization:
Read/Write Access:
PD1.[6:0]:
PD1.7: Reserved
EIES0 (0Ah, 01h)
Initialization:
Read/Write Access:
EIES0.[7:0]: IT[7:0]
______________________________________________________________________________________
External Interrupt Enable 1 Register
EIE1 is cleared to 00h on all forms of reset.
Unrestricted read/write.
Enable External Interrupt Bits 11:8. Setting any of these bits to 1 enables the corresponding
external interrupt. Clearing any of the bits to 0 disables the corresponding interrupt function.
Reserved. Reads return 0.
Port 0 Direction Register
This register is cleared to 00h on all forms of reset.
Unrestricted read/write.
Port 0 Direction Register Bits 7:0. PD0 is used to determine the direction of the Port 0 function. The
port pins are independently controlled by their direction bits. When a bit is set to 1, its corresponding
pin is used as an output; data in the PO register is driven on the pin. When a bit is cleared to 0, its
corresponding pin is used as an input, and allows an external signal to drive the pin. Note that each
port pin has a weak pullup circuit when functioning as an input and the p-channel pullup transistor is
controlled by its respective PO bits. If the PO bit is set to 1, the weak pullup is on; if the PO bit is
cleared to 0, the weak pullup is off and forces the port pin into three-state.
Port 1 Direction Register
This register is cleared to 00h on all forms of reset.
Unrestricted read/write.
Port 1 Direction Register Bits 6:0. PD1 is used to determine the direction of the port 1 function.
The port pins are independently controlled by their direction bit. When a bit is set to 1, its
corresponding pin is used as an output; data in the PO register is driven on the pin. When a bit is
cleared to 0, its corresponding pin is used as an input, and allows an external signal to drive the
pin. Note that each port pin has a weak pullup circuit when functioning as an input and the p-
channel pullup transistor is controlled by its respective PO bits. If the PO bit is set to 1, the weak
pullup is on; if the PO bit is cleared to 0, the weak pullup is off and forces the port pin into three-
state. Special note about P1.6: The RST input function remains enabled on P1.6 unless it is
explicitly disabled (RSTD = 1). This means that the ports control bits (PD, PO) can be used to
generate a reset (e.g., by driving the pin low).
Reserved. Reads return 0.
External Interrupt Edge Select 0 Register
EIES0 is cleared to 00h on all forms of reset.
Unrestricted read/write.
Edge Select for External Interrupt Bits 7:0
ITx = 0: External interrupt x is positive-edge triggered.
ITx = 1: External interrupt x is negative-edge triggered.
Special Function Register Bit Descriptions (continued)

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