MAXQ3108-FFN+ Maxim Integrated Products, MAXQ3108-FFN+ Datasheet - Page 30

• Manufacturer Part Number: MAXQ3108-FFN+
• Description: IC MCU DUAL-CORE 16BIT 28-TSSOP
• Manufacturer: Maxim Integrated Products
• Series: MAXQ™r

Specifications of MAXQ3108-FFN+

• Core Processor: RISC
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 11K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-TSSOP
• Processor Series: MAXQ
• Core: RISC
• Data Bus Width: 16 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, JTAG, SPI
• Maximum Clock Frequency: 10 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 2
• Operating Supply Voltage: 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Low-Power, Dual-Core Microcontroller
30
RTSS (1Ah, 01h)
Initialization:
Read/Write Access:
RTSS.[7:0]:
RTSH (1Bh, 01h)
Initialization:
Read/Write Access:
RTSH.[15:0]:
RTSL (1Ch, 01h)
Initialization:
Read/Write Access:
RTSL.[15:0]:
RSSA (1Dh, 01h)
Initialization:
Read/Write Access:
RSSA.[7:0]:
______________________________________________________________________________________
RTC Subsecond Counter Register (8-Bit Register)
This register is battery backed through POR so long as V
is indeterminate on the very first POR and must be configured initially by the user. This register is
unaffected by other resets.
Write accessible when RTCE = 0 and BUSY = 0. Read accessible at all times, but the value could
be indeterminate if RDY = 0. Software should be careful to read this register only when RDY = 1.
RTC Subsecond Counter Bit 7:0. This ripple counter represents 1/256-second resolution for the
RTC and its content is incremented with each 256Hz clock tick derived from the 32.768kHz
oscillator. When the counter rollover, its output is used to drive the 32-bit second counter.
RTC Second Counter High Register (16-Bit Register)
This register is battery backed through POR so long as V
is indeterminate on the very first POR and must be configured initially by the user. This register is
unaffected by other resets.
Write accessible when RTCE = 0 and BUSY = 0. Read accessible at all times, but the value could
be indeterminate if RDY = 0. Software should be careful to read this register only when RDY = 1.
RTC Second Counter High Bit 15:0. This register contains the most significant bits for the 32-bit
second counter. The RTC is a ripple counter that consists of cascading the 32-bit second counter
and 8-bit subsecond counter (RTSH, RTSL, and RTSS).
RTC Second Counter Low Register (16-Bit Register)
This register is battery backed through POR so long as V
is indeterminate on the very first POR and must be configured initially by the user. This register is
unaffected by other resets.
Write accessible when RTCE = 0 and BUSY = 0. Read accessible at all times, but the value could
be indeterminate if RDY = 0. Software should be careful to read this register only when RDY = 1.
RTC Second Counter Low Bit 15:0. This register contains the least significant bits for the 32-bit
second counter. The RTC is a ripple counter that consists of cascading the 32-bit second counter
and 8-bit subsecond counter (RTSH, RTSL, and RTSS).
RTC Subsecond Alarm Register (8-Bit Register)
This register is battery backed through POR so long as V
is indeterminate on the very first POR and must be configured initially by the user. This register is
unaffected by other resets.
Unrestricted read. Write accessible when BUSY = 0 and either (ASE = 0 or RTCE = 0).
RTC Subsecond Alarm Register Bit 7:0. This register contains the reload value for the subsecond
alarm. The ALSF bit is set when an autoreload occurs.
Special Function Register Bit Descriptions (continued)
BAT(MIN)
BAT(MIN)
BAT(MIN)
BAT(MIN)
< V
< V
< V
< V
BAT
BAT
BAT
BAT
< V
< V
< V
< V
BAT(MAX)
BAT(MAX)
BAT(MAX)
BAT(MAX)
; however, it
; however, it
; however, it
; however, it