MAXQ3108-FFN+ Maxim Integrated Products, MAXQ3108-FFN+ Datasheet - Page 20

• Manufacturer Part Number: MAXQ3108-FFN+
• Description: IC MCU DUAL-CORE 16BIT 28-TSSOP
• Manufacturer: Maxim Integrated Products
• Series: MAXQ™r

Specifications of MAXQ3108-FFN+

• Core Processor: RISC
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 11K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-TSSOP
• Processor Series: MAXQ
• Core: RISC
• Data Bus Width: 16 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, JTAG, SPI
• Maximum Clock Frequency: 10 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 2
• Operating Supply Voltage: 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Low-Power, Dual-Core Microcontroller
20
ADCN.5: ABF5
ADCN.[7:6]: OSR[1:0]
ADCN.8: MD0E
ADCN.9: MD1E
ADCN.10: MD2E
ADCN.11: MDCKS
ADCN.12: IF10E
______________________________________________________________________________________
ADC5 Buffer Full Flag. This bit is set by hardware to indicate that a sample is available from
ADC5. An interrupt request is generated to a CPU if IF45E = 1 and interrupts are not otherwise
masked globally or modularly. This bit is cleared by hardware by a CPU read (either the UserCore
or the DSPCore) of the AD5 output register. The ABF4 and ABF5 flags are set in the same clock
cycle.
Oversampling Rate Bits 1:0. These register bits control the oversampling rate applied by all of the
cubic sinc digital filters (as given in the table below). These bits are writable only when all
Manchester decoders are disabled.
Manchester Decoder 0 Enable. This bit controls whether Manchester decoder 0 and the two
associated cubic sinc filters are enabled or disabled. When MD0E is configured to logic 1,
Manchester decoder 0 and the associated cubic sinc filters are enabled. This is a special case
where enabling the special function input (Manchester decoder input) forces a specific input mode
(single-ended or differential) based upon the PO bit for the port pin corresponding to the Manchester
decoder positive input (e.g., PO2.4 controls the single-ended or differential configuration for
Manchester decoder 0 when MD0E = 1). When the PO bit = 0, single-ended mode is in effect. When
PO bit = 1, differential mode is in effect. When MD0E is configured to logic 0, these hardware
blocks are disabled. This bit is write accessible only to the UserCore.
Manchester Decoder 1 Enable. This bit controls whether Manchester decoder 1 and the two
associated cubic sinc filters are enabled or disabled. When MD1E is configured to logic 1,
Manchester decoder 1 and the associated cubic sinc filters are enabled. This is a special case
where enabling the special function input (Manchester decoder input) forces a specific input mode
(single-ended or differential) based upon the PO bit for the port pin corresponding to the Manchester
decoder positive input (e.g., PO0.3 controls the single-ended or differential configuration for
Manchester decoder 1 when MD1E = 1). When the PO bit = 0, single-ended mode is in effect. When
PO bit = 1, differential mode is in effect. When MD1E is configured to logic 0, these hardware
blocks are disabled. This bit is write accessible only to the UserCore.
Manchester Decoder 2 Enable. This bit controls whether Manchester decoder 2 and the two
associated cubic sinc filters are enabled or disabled. When MD2E is configured to logic 1,
Manchester decoder 2 and the associated cubic sinc filters are enabled. This is a special case
where enabling the special function input (Manchester decoder input) forces a specific input mode
(single-ended or differential) based upon the PO bit for the port pin corresponding to the Manchester
decoder positive input (e.g., PO2.0 controls the single-ended or differential configuration for
Manchester decoder 2 when MD2E = 1). When the PO bit = 0, single-ended mode is in effect. When
PO bit = 1, differential mode is in effect. When MD2E is configured to logic 0, these hardware
blocks are disabled. This bit is write accessible only to the UserCore.
Manchester Decoders Clock Speed Select. This bit must be configured to tell the Manchester
decoders whether a fast or slow bit-stream sampling clock is used. When configured to 0, the
decoders expect that the sampling clock is faster than the clock source being used by the AD02
modulator(s). When configured to 1, the decoders expect that the sampling clock is slower that
than being used by the AD02.
ADC Interrupt Flags 1 and 0 Enable. This bit serves as the local interrupt enable for the ADC cubic
sinc filter output buffers 1 and 0.
Special Function Register Bit Descriptions (continued)
OSR[1:0]
00b
01b
10b
11b
OVERSAMPLING RATE
128
256
32
64