UPD78F1211MC-GAA-AX Renesas Electronics America, UPD78F1211MC-GAA-AX Datasheet - Page 986

• Manufacturer Part Number: UPD78F1211MC-GAA-AX
• Description: MCU 16BIT 78K0R/LX3 38-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1211MC-GAA-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 27
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

27.2 Operation List
Notes 1.
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
984
Instruction
8-bit data
transfer
Group
2.
3.
2. This number of clocks is for when the program is in the internal ROM (flash memory) area. When
Mnemonic
MOV
When the internal RAM area, SFR area, or extended SFR area is accessed, or for an instruction with no
data access.
When the program memory area is accessed.
Except r = A
fetching an instruction from the internal RAM area, the number of clocks is twice the number of clocks
plus 3, maximum.
register (CKC).
r, #byte
saddr, #byte
sfr, #byte
!addr16, #byte
A, r
r, A
A, saddr
saddr, A
A, sfr
sfr, A
A, !addr16
!addr16, A
PSW, #byte
A, PSW
PSW, A
ES, #byte
ES, saddr
A, ES
ES, A
CS, #byte
A, CS
CS, A
A, [DE]
[DE], A
[DE + byte], #byte
A, [DE + byte]
[DE + byte], A
A, [HL]
[HL], A
[HL + byte], #byte
Operands
Note 3
Note 3
Table 27-5. Operation List (1/17)
CHAPTER 27 INSTRUCTION SET
Bytes
2
3
3
4
1
1
2
2
2
2
3
3
3
2
2
2
3
2
2
3
2
2
1
1
3
2
2
1
1
3
User’s Manual U19678EJ1V1UD
Note 1 Note 2
1
1
1
1
1
1
1
1
1
1
1
1
3
1
3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Clocks
−
−
−
−
−
−
−
−
−
−
4
−
−
−
−
−
−
−
−
−
−
−
4
−
−
4
−
4
−
−
r ← byte
(saddr) ← byte
sfr ← byte
(addr16) ← byte
A ← r
r ← A
A ← (saddr)
(saddr) ← A
A ← sfr
sfr ← A
A ← (addr16)
(addr16) ← A
PSW ← byte
A ← PSW
PSW ← A
ES ← byte
ES ← (saddr)
A ← ES
ES ← A
CS ← byte
A ← CS
CS ← A
A ← (DE)
(DE) ← A
(DE + byte) ← byte
A ← (DE + byte)
(DE + byte) ← A
A ← (HL)
(HL) ← A
(HL + byte) ← byte
CPU
) selected by the system clock control
Operation
Z AC CY
×
×
Flag
×
×
×
×