UPD78F1211MC-GAA-AX Renesas Electronics America, UPD78F1211MC-GAA-AX Datasheet - Page 832
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UPD78F1211MC-GAA-AX
Manufacturer Part Number
UPD78F1211MC-GAA-AX
Description
MCU 16BIT 78K0R/LX3 38-SSOP
Manufacturer
Renesas Electronics America
Series
78K0R/Ix3r
Datasheet
1.UPD78F1201MC-CAB-AX.pdf
(1067 pages)
Specifications of UPD78F1211MC-GAA-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
40MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
27
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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14.6 Timing Charts
slave devices as its communication partner.
which specifies the data transfer direction, and then starts serial communication with the slave device.
transmit data is transferred to the SO latch and is output (MSB first) via the SDA0 pin.
830
When using the I
After outputting the slave address, the master device transmits the TRC bit (bit 3 of the IICA status register (IICS)),
Figures 14-32 and 14-33 show timing charts of the data communication.
The IICA shift register (IICA)’s shift operation is synchronized with the falling edge of the serial clock (SCL0). The
Data input via the SDA0 pin is captured into IICA at the rising edge of SCL0.
2
C bus mode, the master device outputs an address via the serial bus to select one of several
CHAPTER 14 SERIAL INTERFACE IICA
User’s Manual U19678EJ1V1UD
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