UPD78F1211MC-GAA-AX Renesas Electronics America, UPD78F1211MC-GAA-AX Datasheet - Page 616

• Manufacturer Part Number: UPD78F1211MC-GAA-AX
• Description: MCU 16BIT 78K0R/LX3 38-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1211MC-GAA-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 27
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

614
Address: F00F0H
(1) Peripheral enable register 0 (PER0)
(2) Serial clock select register 0 (SPS0)
Symbol
PER0
PER0 is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a hardware
macro that is not used is stopped in order to reduce the power consumption and noise.
When serial array unit is used, be sure to set bit 2 (SAU0EN) of this register to 1.
PER0 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears PER0 register to 00H.
Cautions 1. When setting serial array unit, be sure to set SAU0EN bit to 1 first. If SAU0EN = 0, writing
SPS0 register is a 16-bit register that is used to select two types of operation clocks (CK00, CK01) that are
commonly supplied to each channel. CK01 is selected by bits 7 to 4 of SPS0 register , and CK00 is selected
by bits 3 to 0.
Rewriting SPS0 register is prohibited when the register is in operation (when SE0n = 1).
SPS0 register can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of SPS0 register can be set with an 8-bit memory manipulation instruction with SPS0L.
Reset signal generation clears SPS0 register to 0000H.
Notes
RTCEN
SAU0EN
1.
2.
2. After setting bit 2 (SAU0EN) of the PER0 register to 1, be sure to set serial clock select
3. Be sure to clear bits 0, 1, 3, and 6 (78K0R/IB3 : Bits 0, 1, 3, 4, 6, 7, 38-pin and 44-pin
<7>
0
1
After reset: 00H
RTCEN bit is not provided in the 78K0R/IB3. In the 78K0R/IB3, bit 7 of PER0 register is fixed to
0.
IICAEN bit is not provided in the 78K0R/IB3 and 38-pin and 44-pin products of the 78K0R/IC3. In
the 78K0R/IB3 and 38-pin and 44-pin products of the 78K0R/IC3, bit 4 of PER0 register is fixed
to 0.
products of 78K0R/IC3: 0, 1, 3, 4, 6) of PER0 register to 0.
to a control register of serial array unit is ignored, and, even if the register is read, only
the default value is read (except for input switch control register (ISC), noise filter enable
register (NFEN0), port input mode registers (PIM3, PIM7), port output mode registers
(POM3, POM7), port mode registers (PM3, PM7), and port registers (P1, P3, P7)).
register 0 (SPS0) after 4 or more f
Note 1
Stops supply of input clock.
• SFR used by serial array unit cannot be written.
• Serial array unit is in the reset status.
Enables input clock supply.
• SFR used by serial array unit can be read/written.
Figure 13-4. Format of Peripheral Enable Register 0 (PER0)
6
0
R/W
CHAPTER 13 SERIAL ARRAY UNIT
ADCEN
<5>
User’s Manual U19678EJ1V1UD
Control of serial array unit input clock supply
IICAEN
<4>
CLK
Note 2
clocks have elapsed.
3
0
SAU0EN
<2>
1
0
0
0