UPD78F1211MC-GAA-AX Renesas Electronics America, UPD78F1211MC-GAA-AX Datasheet - Page 549
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UPD78F1211MC-GAA-AX
Manufacturer Part Number
UPD78F1211MC-GAA-AX
Description
MCU 16BIT 78K0R/LX3 38-SSOP
Manufacturer
Renesas Electronics America
Series
78K0R/Ix3r
Datasheet
1.UPD78F1201MC-CAB-AX.pdf
(1067 pages)
Specifications of UPD78F1211MC-GAA-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
40MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
27
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Address: FFF9FH
Address: FFF90H
Address: FFF91H
(4) Real-time counter control register 2 (RTCC2)
(5) Sub-count register (RSUBC)
RSUBC
RSUBC
RTCC2
Symbol
Symbol
Symbol
The RTCC2 register is an 8-bit register that is used to control the interval interrupt function.
RTCC2 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
The RSUBC register is a 16-bit register that counts the reference time of 1 second of the real-time counter. It
takes a value of 0000H to 7FFFH and counts 1 second with a clock of 32.768 kHz.
RSUBC can be set by a 16-bit memory manipulation instruction.
Reset signal generation clears this register to 0000H.
Cautions 1. When a correction is made by using the SUBCUD register, the value may become 8000H
Cautions 1. Change ICT2, ICT1, and ICT0 when RINTE = 0.
SUBC15
SUBC7
RINTE
RINTE
2. This register is also cleared by reset effected by writing the second count register.
3. The value read from this register is not guaranteed if it is read during operation, because
<7>
0
1
1
1
1
1
1
1
7
7
After reset: 0000H
After reset: 0000H
After reset: 00H
or more.
a value that is changing is read.
Figure 9-5. Format of Real-Time Counter Control Register 2 (RTCC2)
2. Be sure to clear bits 3 to 6 to 0.
SUBC14
SUBC6
ICT2
Figure 9-6. Format of Sub-Count Register (RSUBC)
×
0
0
0
0
1
1
1
6
0
6
6
R/W
R
R
CHAPTER 9 REAL-TIME COUNTER
SUBC13
SUBC5
ICT1
×
0
0
1
1
0
0
1
5
0
5
5
User’s Manual U19678EJ1V1UD
SUBC12
SUBC4
ICT0
×
0
1
0
1
0
1
×
4
0
4
4
Interval interrupt is not generated.
2
2
2
2
2
2
2
6
7
8
9
10
11
12
/f
/f
/f
/f
SUBC11
/f
/f
/f
SUBC3
XT
XT
XT
XT
XT
XT
XT
(1.953125 ms)
(3.90625 ms)
(7.8125 ms)
(15.625 ms)
3
0
3
3
(31.25 ms)
(62.5 ms)
(125 ms)
Interval interrupt (INTRTCI) selection
SUBC10
SUBC2
ICT2
2
2
2
SUBC1
SUBC9
ICT1
1
1
1
SUBC0
SUBC8
ICT0
0
0
0
547
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