UPD78F0513AGA-GAM-AX Renesas Electronics America, UPD78F0513AGA-GAM-AX Datasheet - Page 767

• Manufacturer Part Number: UPD78F0513AGA-GAM-AX
• Description: MCU 8BIT 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0513AGA-GAM-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 41
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
Call/return
Stack
manipulate
Unconditional
branch
Conditional
branch
Instruction
Notes 1.
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
Group
2.
CALL
CALLF
CALLT
BRK
RET
RETI
RETB
PUSH
POP
MOVW
BR
BC
BNC
BZ
BNZ
Mnemonic
2. This clock cycle applies to the internal ROM program.
When the internal high-speed RAM area is accessed or for an instruction with no data access
When an area except the internal high-speed RAM area is accessed
register (PCC).
!addr16
!addr11
[addr5]
PSW
rp
PSW
rp
SP, #word
SP, AX
AX, SP
!addr16
$addr16
AX
$addr16
$addr16
$addr16
$addr16
Operands
Bytes
3
2
1
1
1
1
1
1
1
1
1
4
2
2
3
2
2
2
2
2
2
Note 1
7
5
6
6
6
6
6
2
4
2
4
−
−
−
6
6
8
6
6
6
6
Clocks
Note 2
10
−
−
−
−
−
−
−
−
−
−
−
8
8
−
−
−
−
−
−
−
(SP − 1) ← (PC + 3)
PC ← addr16, SP ← SP − 2
(SP − 1) ← (PC + 2)
PC
SP ← SP − 2
(SP − 1) ← (PC + 1)
PC
SP ← SP − 2
(SP − 1) ← PSW, (SP − 2) ← (PC + 1)
(SP − 3) ← (PC + 1)
PC
PC
SP ← SP + 2
PC
PSW ← (SP + 2), SP ← SP + 3
PC
PSW ← (SP + 2), SP ← SP + 3
(SP − 1) ← PSW, SP ← SP − 1
(SP − 1) ← rp
SP ← SP − 2
PSW ← (SP), SP ← SP + 1
rp
SP ← SP + 2
SP ← word
SP ← AX
AX ← SP
PC ← addr16
PC ← PC + 2 + jdisp8
PCH ← A, PC
PC ← PC + 2 + jdisp8 if CY = 1
PC ← PC + 2 + jdisp8 if CY = 0
PC ← PC + 2 + jdisp8 if Z = 1
PC ← PC + 2 + jdisp8 if Z = 0
H
15 − 11
H
L
H
H
H
← (SP + 1), rp
← (003EH), SP ← SP − 3, IE ← 0
← (addr5 + 1), PC
← (SP + 1), PC
← (SP + 1), PC
← (SP + 1), PC
← 00001, PC
CPU
H
) selected by the processor clock control
L
CHAPTER 29 INSTRUCTION SET
, (SP − 2) ← rp
← X
Operation
L
← (SP),
H
H
H
L
L
L
L
, PC
, (SP − 2) ← (PC + 3)
, (SP − 2) ← (PC + 2)
, (SP − 2) ← (PC + 1)
← (SP),
← (SP),
← (SP),
10 − 0
L
← (addr5),
H
← addr11,
← (003FH),
L
,
H
,
L
L
L
,
,
,
Z AC CY
R R R
R R R
R R R
Flag
767