UPD78F0513AGA-GAM-AX Renesas Electronics America, UPD78F0513AGA-GAM-AX Datasheet - Page 669

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UPD78F0513AGA-GAM-AX

Manufacturer Part Number
UPD78F0513AGA-GAM-AX
Description
MCU 8BIT 48-LQFP
Manufacturer
Renesas Electronics America
Series
78K0/Kx2r
Datasheet

Specifications of UPD78F0513AGA-GAM-AX

Core Processor
78K/0
Core Size
8-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
41
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD78F0513AGA-GAM-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
UPD78F0513AGA-GAM-AX
Manufacturer:
NEC
Quantity:
20 000
78K0/Kx2
22.2 Standby Function Operation
22.2.1 HALT mode
(1) HALT mode
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
The HALT mode is set by executing the HALT instruction. HALT mode can be set regardless of whether the CPU
clock before the setting was the high-speed system clock, internal high-speed oscillation clock, or subsystem clock
The operating statuses in the HALT mode are shown below.
Note The 78K0/KB2 is not provided with a subsystem clock.
Address: FFA4H
Symbol
OSTS
Remark f
Cautions 1. To set the STOP mode when the X1 clock is used as the CPU clock, set OSTS before
Figure 22-2. Format of Oscillation Stabilization Time Select Register (OSTS)
OSTS2
7
0
0
0
0
1
1
After reset: 05H
2. Do not change the value of the OSTS register during the X1 clock oscillation
3. The oscillation stabilization time counter counts up to the oscillation stabilization
4. The X1 clock oscillation stabilization wait time does not include the time until clock
X
: X1 clock oscillation frequency
Other than above
executing the STOP instruction.
stabilization time.
time set by OSTS. If the STOP mode is entered and then released while the internal
high-speed oscillation clock is being used as the CPU clock, set the oscillation
stabilization time as follows.
Note, therefore, that only the status up to the oscillation stabilization time set by
OSTS is set to OSTC after STOP mode is released.
oscillation starts (“a” below).
OSTS1
• Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time set
6
0
0
1
1
0
0
by OSTS
X1 pin voltage
waveform
R/W
OSTS0
5
0
1
0
1
0
1
STOP mode release
2
2
2
2
2
Setting prohibited
11
13
14
15
16
/f
/f
/f
/f
/f
X
X
X
X
X
4
0
a
Oscillation stabilization time selection
3
0
204.8
819.2
1.64 ms
3.27 ms
6.55 ms
CHAPTER 22 STANDBY FUNCTION
f
X
μ
μ
OSTS2
= 10 MHz
s
s
2
OSTS1
102.4
409.6
819.2
1.64 ms
3.27 ms
1
f
X
μ
μ
μ
= 20 MHz
s
s
s
OSTS0
0
Note
669
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