UPD78F0513AGA-GAM-AX Renesas Electronics America, UPD78F0513AGA-GAM-AX Datasheet - Page 693

• Manufacturer Part Number: UPD78F0513AGA-GAM-AX
• Description: MCU 8BIT 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0513AGA-GAM-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 41
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
24.2 Configuration of Power-on-Clear Circuit
24.3 Operation of Power-on-Clear Circuit
(1) In 1.59 V POC mode (option byte: POCMODE = 0)
(2) In 2.7 V/1.59 V POC mode (option byte: POCMODE = 1)
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
The block diagram of the power-on-clear circuit is shown in Figure 24-1.
• An internal reset signal is generated on power application. When the supply voltage (V
• The supply voltage (V
• An internal reset signal is generated on power application. When the supply voltage (V
• The supply voltage (V
The timing of generation of the internal reset signal by the power-on-clear circuit and low-voltage detector is shown
below.
voltage (V
internal reset signal is generated. It is released when V
voltage (V
internal reset signal is generated. It is released when V
POC
DDPOC
= 1.59 V ±0.15 V), the reset status is released.
V
= 2.7 V ±0.2 V), the reset status is released.
DD
DD
DD
) and detection voltage (V
) and detection voltage (V
Figure 24-1. Block Diagram of Power-on-Clear Circuit
Reference
voltage
source
+
V
DD
POC
POC
DD
DD
= 1.59 V ±0.15 V) are compared. When V
= 1.59 V ±0.15 V) are compared. When V
≥ V
≥ V
POC
DDPOC
CHAPTER 24 POWER-ON-CLEAR CIRCUIT
.
.
Internal reset signal
DD
DD
) exceeds the detection
) exceeds the detection
DD
DD
< V
< V
POC
POC
, the
, the
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