UPD78F0513AGA-GAM-AX Renesas Electronics America, UPD78F0513AGA-GAM-AX Datasheet - Page 482

• Manufacturer Part Number: UPD78F0513AGA-GAM-AX
• Description: MCU 8BIT 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0513AGA-GAM-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 41
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
1. Normal SBF reception (stop bit is detected with a width of more than 10.5 bits)
2. SBF reception error (stop bit is detected with a width of 10.5 bits or less)
Remark R
(i)
SBF reception
When the device is used in LIN communication operation, the SBF (Synchronous Break Field) reception control
function is used for reception. For the reception operation of LIN, see Figure 15-2 LIN Reception Operation.
Reception is enabled when bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6)
is set to 1 and then bit 5 (RXE6) of ASIM6 is set to 1. SBF reception is enabled when bit 6 (SBRT6) of
asynchronous serial interface control register 6 (ASICL6) is set to 1. In the SBF reception enabled status, the
R
When the start bit has been detected, reception is started, and serial data is sequentially stored in the receive
shift register 6 (RXS6) at the set baud rate. When the stop bit is received and if the width of SBF is 11 bits or
more, a reception completion interrupt request (INTSR6) is generated as normal processing. At this time, the
SBRF6 and SBRT6 bits are automatically cleared, and SBF reception ends. Detection of errors, such as OVE6,
PE6, and FE6 (bits 0 to 2 of asynchronous serial interface reception error status register 6 (ASIS6)) is
suppressed, and error detection processing of UART communication is not performed. In addition, data transfer
between receive shift register 6 (RXS6) and receive buffer register 6 (RXB6) is not performed, and the reset
value of FFH is retained. If the width of SBF is 10 bits or less, an interrupt does not occur as error processing
after the stop bit has been received, and the SBF reception mode is restored. In this case, the SBRF6 and
SBRT6 bits are not cleared.
INTSR6
/SBRF6
X
SBRT6
D6 pin is sampled and the start bit is detected in the same manner as the normal reception enable status.
R
SBRT6: Bit 6 of asynchronous serial interface control register 6 (ASICL6)
SBRF6: Bit 7 of ASICL6
INTSR6: Reception completion interrupt request
X
INTSR6
/SBRF6
D6
SBRT6
X
D6:
R
X
D6
“0”
R
X
D6 pin (input)
1
1
2
2
3
Figure 15-23. SBF Reception
3
4
4
5
5
6
6
CHAPTER 15 SERIAL INTERFACE UART6
7
7
8
8
9
9
10
10
11
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