UPD78F0513AGA-GAM-AX Renesas Electronics America, UPD78F0513AGA-GAM-AX Datasheet - Page 196

• Manufacturer Part Number: UPD78F0513AGA-GAM-AX
• Description: MCU 8BIT 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0513AGA-GAM-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 41
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
5.2.9 Port 12
Note OCD0A and OCD0B are provided to the products with an on-chip debug function (
Remark √: Mounted, −: Not mounted
mode register 12 (PM12). When used as an input port only for P120, use of an on-chip pull-up resistor can be specified
by pull-up resistor option register 12 (PU12).
connecting resonator for main system clock, connecting resonator for subsystem clock, external clock input for main
system clock, and external clock input for subsystem clock.
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
P120/INTP0/EXLVI
P121/X1/OCD0A
P122/X2/EXCLK/
OCD0B
P123/XT1
P124/XT2/EXCLKS
Port 12 is an I/O port with an output latch. Port 12 can be set to the input mode or output mode in 1-bit units using port
This port can also be used as pins for external interrupt request input, potential input for external low-voltage detection,
Reset signal generation sets port 12 to input mode.
Figures 5-22 and 5-23 show block diagrams of port 12.
Caution
only.
Note
1. When using the P121 to P124 pins to connect a resonator for the main system clock (X1, X2) or
Note
subsystem clock (XT1, XT2), or to input an external clock for the main system clock (EXCLK) or
subsystem clock (EXCLKS), the X1 oscillation mode, XT1 oscillation mode, or external clock
input mode must be set by using the clock operation mode select register (OSCCTL) (for details,
see 6.3 (1) Clock operation mode select register (OSCCTL) and (3) Setting of operation mode for
subsystem clock pin). The reset value of OSCCTL is 00H (all of the P121 to P124 pins are I/O port
pins). At this time, setting of the PM121 to PM124 and P121 to P124 pins is not necessary.
78K0/KB2
√
√
√
−
−
78K0/KC2
78K0/KD2
whose flash
memory is
Products
less than
32 KB
√
√
√
√
√
78K0/KE2
CHAPTER 5 PORT FUNCTIONS
memory is at
whose flash
Products
μ
48 KB
PD78F05xxD and 78F05xxDA)
least
78K0/KF2
196