M37632EFFP#U2 Renesas Electronics America, M37632EFFP#U2 Datasheet - Page 39

• Manufacturer Part Number: M37632EFFP#U2
• Description: IC 740 MCU 80QFP
• Manufacturer: Renesas Electronics America

Specifications of M37632EFFP#U2

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADC
Notes 1: When T=1, add 3 to the cycle number.
Rev.2.00 Nov 14, 2006
REJ09B0322-0200
Addressing mode
Immediate
Zero page
Zero page X
Absolute
Absolute X
Absolute Y
(Indirect X)
(Indirect Y)
Status flag: N :
Operation :
Function :
2: When ADC instruction is executed in decimal operation mode (D = 1),
execute at least one instruction after the ADC instruction before
executing a SEC, CLC, or CLD instruction.
In decimal operation mode, the N, V, Z flags are invalid.
V :
B :
D :
C :
T :
Z :
When (T) = 0, (A) ← (A) + (M) + (C)
When T = 0, this instruction adds the contents M, C, and A;
and stores the results in A and C.
When T = 1, this instruction adds the contents of M(X), M and
C; and stores the results in M(X) and C. When T=1, the
contents of A remain unchanged, but the contents of status
flags are changed.
M(X) represents the contents of memory where is indicated by
X.
I :
∆ADC∆#$nn
∆ADC∆$zz
∆ADC∆$zz,X
∆ADC∆$hhll
∆ADC∆$hhll,X
∆ADC∆$hhll,Y
∆ADC∆($zz,X)
∆ADC∆($zz),Y
page 31 of 185
N is 1 when bit 7 is 1 after the operation; otherwise it is
0.
V is 1 when the operation result exceeds +127 or –128;
otherwise it is 0.
No change
No change
No change
No change
Z is 1 when the operation result is 0; otherwise it is 0.
C is 1 when the result of a binary addition exceeds 255 or
when the result of a decimal addition exceeds 99;
otherwise it is 0.
(T) = 1, (M(X)) ← (M(X)) + (M) + (C)
Statement
AD
D WITH
69
65
75
6D
7D
79
61
71
Machine codes
16
16
16
16
16
16
16
16
C
, nn
, zz
, zz
, ll
, zz
, zz
, ll
, ll
ARRY
16
16
16
16
16
16
16
16
, hh
, hh
, hh
16
16
16
Byte number
2
2
2
3
3
3
2
2
ADC
Cycle number
2
3
4
4
5
5
6
6