M37632EFFP#U2 Renesas Electronics America, M37632EFFP#U2 Datasheet - Page 110

• Manufacturer Part Number: M37632EFFP#U2
• Description: IC 740 MCU 80QFP
• Manufacturer: Renesas Electronics America

Specifications of M37632EFFP#U2

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

INSTRUCTIONS
3.4 Instructions Related to Interrupt Handling and Subroutine Processing
3.4.1 Instructions Related to Interrupt Handling
3.4.2 Instructions Related to Interrupt Control
Rev.2.00 Nov 14, 2006
REJ09B0322-0200
Instructions Related to Interrupt Processing and Subroutine Processing
When an interrupt is accepted, the contents of the processor status register are pushed onto
the memory location indicated by the stack pointer. There is therefore no need to execute the
PHP instruction.
If it is necessary to save the contents of the accumulator, the PHA instruction should be
executed within an interrupt routine (before any instruction that manipulates the accumulator).
Whenever a stack operation instruction such as PHA is executed within an interrupt routine,
make sure that instructions such as PLA that affect the stack operation instruction are also
executed within the same interrupt routine.
Execute the RTI instruction to return from the interrupt routine.
The factors that control an interrupt are the interrupt disable flag (I) as well as the interrupt
enable bit and request bit corresponding to the interrupt source. (This does not apply to
software interrupts triggered by the BRK instruction.)
(1) Disabling Interrupts
(2) Enabling Interrupts
(3) Clearing Interrupt Requests
While the interrupt disable flag (I) is “0”, if the interrupt request bit is cleared to “0” and
the interrupt enable bit is cleared to “0” at the same time using an instruction such as
LDM, the interrupt will actually be enabled before the request bit is cleared to “0”, causing
the interrupt to be accepted.
To prevent this, use an instruction such as CLB to clear the request bit to “0” first, then
enable the interrupt.
An interrupt may be disabled by setting the interrupt disable flag (I) to “1” using the SEI
instruction or by using an instruction such as LDM or CLB (a variety of other instructions
can be used as well) to clear the interrupt enable bit to “0”.
An interrupt may be enabled by setting the interrupt enable bit to “1” using an instruction
such as LDM or SEB, and by using the CLI instruction to clear the interrupt disable flag
(I) to “0”.
When an interrupt is generated, the interrupt request bit corresponding to the interrupt
source is set to “1” automatically. The interrupt request bit is cleared to “0” when the
interrupt is accepted. Therefore, there is no need to clear the interrupt request bit (within
an interrupt routine) by means of a user program.
If interrupt generation occurs while an interrupt is disabled, the interrupt request bit is set
to “1”. If, under this condition, the interrupt is subsequently enabled (the interrupt disable
flag (I) is cleared to “0” and the interrupt enable bit is set to “1”), the interrupt is
accepted. To prevent an interrupt from being accepted in such a case, use an instruction
such as LDM or CLB to clear the interrupt request bit to “0” before enabling the interrupt.
In such cases, the following point should be considered.
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