M37632EFFP#U2 Renesas Electronics America, M37632EFFP#U2 Datasheet - Page 12

• Manufacturer Part Number: M37632EFFP#U2
• Description: IC 740 MCU 80QFP
• Manufacturer: Renesas Electronics America

Specifications of M37632EFFP#U2

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CENTRAL PROCESSING UNIT
2.4 Program Counter (PC)
The Program Counter is a sixteen-bit counter consisting of PC
eight-bit registers. The contetnts of the Program Counter indicates the address which an
instruction to be executed next is stored.
The 740 Family uses a stored program system; to start a new operation it is necessary to
transfer the instruction and relevant data from memory to the CPU.
Normally the Program Counter is used to indicate the next memory address. After each
instruction is executed, the next instruction required is read. This cycle is repeated until the
program is finished.
2.5 Processor Status Register (PS)
The Processor Status Register is an eight-bit register consisting of 5 flags which indicate the
status of arithmetic operations and 3 flags which determine operation. Immediately after a
reset, only the interrupt disable flag is set to “1,” and the other flags are undefined. Therefore,
initialize the flags that effect program execution. Especially, initialize the T and D flags because
of their effect on operation.
Each of these flags is described below. Table 2.5.1 lists the instructions to set/clear each flag.
Refer to the section “Appendix 2 MACHINE LANGUAGE INSTRUCTION TABLE” or “3.3
INSTRUCTIONS” for details on when these flags are altered.
[ Carry flag C ] ------------------------------------------------------ Bit 0
[ Zero flag Z ] ------------------------------------------------------- Bit 1
[ Interrupt disable flag I ] ---------------------------------------- Bit 2
[ Decimal mode flag D ] ----------------------------------------- Bit 3
[ Break flag B ] ----------------------------------------------------- Bit 4
Rev.2.00 Nov 14, 2006
REJ09B0322-0200
The control of the Program Counter of the 740 Family is almost fully automatic. However,
This flag stores any carry or borrow from the Arithmetic Logic Unit (ALU) after an arithmetic
operation and is also changed by the Shift or Rotate instruction.
This flag is set by the SEC instruction and is cleared by the CLC instruction.
This flag is set when the result of an arithmetic operation or data transfer is “0” and is
cleared by any other result.
This flag disables interrupts when it is set to “1.” This flag immediately becomes “1” when
an interrupt is received.
This flag is set by the SEI instruction and is cleared by the CLI instruction.
This flag determines whether addition and subtraction are performed in binary or decimal
notation. Addition and subtraction are performed in binary notation when this flag is set to
“0” and as a 2-digit, 1-word decimal numeral when set to “1.” Decimal notation correction
is performed automatically at this time.
This flag is set by the SED instruction and is cleared by the CLD instruction.
Only the ADC and SBC instructions are used for decimal arithmetic operations.
Note that the flags N, V and Z are invalid when decimal arithmetic operations are per-
formed by these instructions.
This flag determines whether an interrupt was generated with the BRK instruction. When a
BRK instruction interrupt occurs, the flag B is set to “1” and saved to the stack; for all other
interrupts the flag is set to “0” and saved to the stack.
caution must be exercised to avoid differences between program flow and Program
Counter contents when using the Stack Pointer or directly altering the contents of the
Program Counter.
page 4 of 185
Processor Status Register (PS)
H
Program Counter (PC)
and PC
L
, which are each