M37632EFFP#U2 Renesas Electronics America, M37632EFFP#U2 Datasheet - Page 120

• Manufacturer Part Number: M37632EFFP#U2
• Description: IC 740 MCU 80QFP
• Manufacturer: Renesas Electronics America

Specifications of M37632EFFP#U2

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

APPENDIX 1
APPENDIX 1. Instruction Cycles in each Addressing Mode
Clock φ controls the system timing of 740 Family. The SYNC signal and the value of PC
(Program Counter) are output in every instruction fetch cycle. The Op-Code is fetched during
the next half-period of φ . The instruction decoder of CPU decodes this Op-Code and
determines the following how to execute the instruction. The instruction timings of all address-
ing modes are described on the following pages.
The φ , SYNC, R/W (RD, WR), ADDR (ADDR
indicate the status of the internal bus. These signals cannot be seen directly in single-chip
mode, but they can be checked on products that support use of microprocessor mode.
The combination of these signals differs according to the microcomputer’s type. The following
table lists the valid signal for each product.
Valid signal for each product
Note: Only 80-pin version.
Rev.2.00 Nov 14, 2006
REJ09B0322-0200
M507XX
M509XX
M374XX
(Except M37451)
M38XXX
M375XX
M372XX
M371XX
M37451
M50734
Type
φ
page 112 of 185
SYNC
Instruction Cycles in each Addressing Mode
R/W
(Note)
RD
L
, ADDR
(Note)
WR
H
), and DATA signals in these figures
ADDR DATA ADDR
H
ADDR
L
/DATA